3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * Modified By Conn Clark to work with Esteem 192E 7/31/00
31 /* ------------------------------------------------------------------------- */
33 static long int dram_size ( long int *base, long int maxsize);
35 /* ------------------------------------------------------------------------- */
37 #define _NOT_USED_ 0xFFFFFFFF
39 const uint sdram_table[] =
42 * Single Read. (Offset 0 in UPMA RAM)
44 * active, NOP, read, precharge, NOP */
45 0x0F27CC04, 0x0EAECC04, 0x00B98C04, 0x00F74C00,
46 0x11FFCC05, /* last */
48 * SDRAM Initialization (offset 5 in UPMA RAM)
50 * This is no UPM entry point. The following definition uses
51 * the remaining space to establish an initialization
52 * sequence, which is executed by a RUN command.
55 0x0F0A8C34, 0x1F354C37, /* last */
57 _NOT_USED_, /* Not used */
60 * Burst Read. (Offset 8 in UPMA RAM)
61 * active, NOP, read, NOP, NOP, NOP, NOP, NOP */
62 0x0F37CC04, 0x0EFECC04, 0x00FDCC04, 0x00FFCC00,
63 0x00FFCC00, 0x01FFCC00, 0x0FFFCC00, 0x1FFFCC05, /* last */
64 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
65 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
67 * Single Write. (Offset 18 in UPMA RAM)
68 * active, NOP, write, NOP, precharge, NOP */
69 0x0F27CC04, 0x0EAE8C00, 0x01BD4C04, 0x0FFB8C04,
70 0x0FF74C04, 0x1FFFCC05, /* last */
71 _NOT_USED_, _NOT_USED_,
73 * Burst Write. (Offset 20 in UPMA RAM)
74 * active, NOP, write, NOP, NOP, NOP, NOP, NOP */
75 0x0F37CC04, 0x0EFE8C00, 0x00FD4C00, 0x00FFCC00,
76 0x00FFCC00, 0x01FFCC04, 0x0FFFCC04, 0x1FFFCC05, /* last */
77 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
78 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
80 * Refresh (Offset 30 in UPMA RAM)
81 * precharge, NOP, auto_ref, NOP, NOP, NOP */
82 0x0FF74C34, 0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34,
83 0x0FFFCCB4, 0x1FFFCC35, /* last */
84 _NOT_USED_, _NOT_USED_,
85 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
87 * Exception. (Offset 3c in UPMA RAM)
89 0x0FFB8C00, 0x1FF74C03, /* last */
90 _NOT_USED_, _NOT_USED_
93 /* ------------------------------------------------------------------------- */
97 * Check Board Identity:
100 int checkboard (void)
102 puts ("Board: Esteem 192E\n");
106 /* ------------------------------------------------------------------------- */
109 long int initdram (int board_type)
111 volatile immap_t *immap = (immap_t *)CFG_IMMR;
112 volatile memctl8xx_t *memctl = &immap->im_memctl;
113 long int size_b0, size_b1;
116 * Explain frequency of refresh here
119 memctl->memc_mptpr = 0x0200; /* divide by 32 */
121 memctl->memc_mamr = 0x18003112; /*CFG_MAMR_8COL;*/ /* 0x18005112 TODO: explain here */
123 upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
126 * Map cs 2 and 3 to the SDRAM banks 0 and 1 at
127 * preliminary addresses - these have to be modified after the
128 * SDRAM size has been determined.
131 memctl->memc_or2 = CFG_OR2_PRELIM; /* not defined yet */
132 memctl->memc_br2 = CFG_BR2_PRELIM;
134 memctl->memc_or3 = CFG_OR3_PRELIM;
135 memctl->memc_br3 = CFG_BR3_PRELIM;
138 /* perform SDRAM initializsation sequence */
139 memctl->memc_mar = 0x00000088;
141 memctl->memc_mcr = 0x80004830; /* SDRAM bank 0 execute 8 refresh */
143 memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
146 memctl->memc_mcr = 0x80006830; /* SDRAM bank 1 execute 8 refresh */
148 memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
151 memctl->memc_mamr = CFG_MAMR_8COL; /* 0x18803112 start refresh timer TODO: explain here */
153 /* printf ("banks 0 and 1 are programed\n"); */
156 * Check Bank 0 Memory Size for re-configuration
160 size_b0 = dram_size ((ulong *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
162 size_b1 = dram_size ((ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
165 printf ("\nbank 0 size %lu\nbank 1 size %lu\n",size_b0,size_b1);
168 /* printf ("bank 1 size %u\n",size_b1); */
173 * Adjust refresh rate if bank 0 isn't stuffed
176 memctl->memc_mptpr = 0x0400; /* divide by 64 */
177 memctl->memc_br3 &= 0x0FFFFFFFE;
180 * Adjust OR2 for size of bank 0
182 memctl->memc_or2 |= 7 * size_b0;
188 if(size_b0 < size_b1) {
189 memctl->memc_br2 &= 0x00007FFE;
190 memctl->memc_br3 &= 0x00007FFF;
193 * Adjust OR3 for size of bank 1
195 memctl->memc_or3 |= 15 * size_b1;
198 * Adjust OR2 for size of bank 0
200 memctl->memc_or2 |= 15 * size_b0;
202 memctl->memc_br2 += (size_b1 + 1);
207 memctl->memc_br3 &= 0x00007FFE;
211 * Adjust OR2 for size of bank 0
213 memctl->memc_or2 |= 15 * size_b0;
216 * Adjust OR3 for size of bank 1
218 memctl->memc_or3 |= 15 * size_b1;
220 memctl->memc_br3 += (size_b0 + 1);
227 /* before leaving set all unused i/o pins to outputs */
230 * --*Unused Pin List*--
232 * group/port bit number
233 * IP_B 0,1,3,4,5 Taken care of in pcmcia-cs-x.x.xx
236 * PC 4,5,6,7,10,11,12,13,14,15
242 * --*Pin Used for I/O List*--
244 * port input bit number output bit number either
246 * PD 3,4 8,9,10,11,12,13,14,15
251 immap->im_ioport.iop_papar &= ~0x05C3; /* set pins as io */
252 immap->im_ioport.iop_padir |= 0x05C3; /* set pins as output */
253 immap->im_ioport.iop_paodr &= 0x0008; /* config pins 9 & 14 as normal outputs */
254 immap->im_ioport.iop_padat |= 0x05C3; /* set unused pins as high */
256 immap->im_cpm.cp_pbpar &= ~0x00001331; /* set unused port b pins as io */
257 immap->im_cpm.cp_pbdir |= 0x00001331; /* set unused port b pins as output */
258 immap->im_cpm.cp_pbodr &= ~0x00001331; /* config bits 18,22,23,26,27 & 31 as normal outputs */
259 immap->im_cpm.cp_pbdat |= 0x00001331; /* set T/E LED, /NV_CS, & /POWER_ADJ_CS and the rest to a high */
261 immap->im_ioport.iop_pcpar &= ~0x0F3F; /* set unused port c pins as io */
262 immap->im_ioport.iop_pcdir |= 0x0F3F; /* set unused port c pins as output */
263 immap->im_ioport.iop_pcso &= ~0x0F3F; /* clear special purpose bit for unused port c pins for clarity */
264 immap->im_ioport.iop_pcdat |= 0x0F3F; /* set unused port c pins high*/
266 immap->im_ioport.iop_pdpar &= 0xE000; /* set pins as io */
267 immap->im_ioport.iop_pddir &= 0xE000; /* set bit 3 & 4 as inputs */
268 immap->im_ioport.iop_pddir |= 0x07FF; /* set bits 5 - 15 as outputs */
269 immap->im_ioport.iop_pddat = 0x0055; /* set alternating pattern on test port */
272 return (size_b0 + size_b1);
275 /* ------------------------------------------------------------------------- */
278 * Check memory range for valid RAM. A simple memory test determines
279 * the actually available RAM size between addresses `base' and
280 * `base + maxsize'. Some (not all) hardware errors are detected:
281 * - short between address lines
282 * - short between data lines
285 static long int dram_size ( long int *base, long int maxsize)
288 volatile long int *addr;
291 for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
292 addr = base + cnt; /* pointer arith! */
297 /* write 0 to base address */
301 /* check at base address */
302 if ((val = *addr) != 0) {
306 for (cnt = 1; ; cnt <<= 1) {
307 addr = base + cnt; /* pointer arith! */
312 return (cnt * sizeof(long));