2 * (C) Copyright 2001-2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
30 /* ------------------------------------------------------------------------- */
36 extern void lxt971_no_sleep(void);
38 /* fpga configuration data - gzip compressed and generated by bin2c */
39 const unsigned char fpgadata[] =
45 * include common fpga code (for esd boards)
47 #include "../common/fpga.c"
50 /* logo bitmap data - gzip compressed and generated by bin2c */
51 unsigned char logo_bmp_320[] =
53 #include "logo_320_240_4bpp.c"
56 unsigned char logo_bmp_640[] =
58 #include "logo_640_480_24bpp.c"
63 * include common lcd code (for esd boards)
65 #include "../common/lcd.c"
67 #include "../common/s1d13704_320_240_4bpp.h"
68 #include "../common/s1d13806_320_240_4bpp.h"
69 #include "../common/s1d13806_640_480_16bpp.h"
72 int board_early_init_f (void)
75 * IRQ 0-15 405GP internally generated; active high; level sensitive
76 * IRQ 16 405GP internally generated; active low; level sensitive
78 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
79 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
80 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
81 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
82 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
83 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
84 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
86 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
87 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
88 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
89 mtdcr(UIC0PR, 0xFFFFFFB5); /* set int polarities */
90 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
91 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
92 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
95 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
97 mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
102 int misc_init_r (void)
104 unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
105 unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
106 unsigned short *lcd_contrast =
107 (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 4);
108 unsigned short *lcd_backlight =
109 (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 6);
111 ulong len = sizeof(fpgadata);
117 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
118 if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
119 printf ("GUNZIP ERROR - must RESET board to recover\n");
120 do_reset (NULL, 0, 0, NULL);
123 status = fpga_boot(dst, len);
125 printf("\nFPGA: Booting failed ");
127 case ERROR_FPGA_PRG_INIT_LOW:
128 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
130 case ERROR_FPGA_PRG_INIT_HIGH:
131 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
133 case ERROR_FPGA_PRG_DONE:
134 printf("(Timeout: DONE not high after programming FPGA)\n ");
138 /* display infos on fpgaimage */
140 for (i=0; i<4; i++) {
142 printf("FPGA: %s\n", &(dst[index+1]));
147 for (i=20; i>0; i--) {
148 printf("Rebooting in %2d seconds \r",i);
149 for (index=0;index<1000;index++)
153 do_reset(NULL, 0, 0, NULL);
158 /* display infos on fpgaimage */
160 for (i=0; i<4; i++) {
162 printf("%s ", &(dst[index+1]));
170 * Reset FPGA via FPGA_INIT pin
172 out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
173 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~FPGA_INIT); /* reset low */
174 udelay(1000); /* wait 1ms */
175 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | FPGA_INIT); /* reset high */
176 udelay(1000); /* wait 1ms */
179 * Reset external DUARTs
181 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */
182 udelay(10); /* wait 10us */
183 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */
184 udelay(1000); /* wait 1ms */
187 * Set NAND-FLASH GPIO signals to default
189 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
190 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
193 * Setup EEPROM write protection
195 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
196 out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
199 * Enable interrupts in exar duart mcr[3]
201 out_8(duart0_mcr, 0x08);
202 out_8(duart1_mcr, 0x08);
205 * Init lcd interface and display logo
207 str = getenv("bd_type");
208 if (strcmp(str, "voh405_bw") == 0) {
210 lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
211 regs_13704_320_240_4bpp,
212 sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
213 logo_bmp_320, sizeof(logo_bmp_320));
214 } else if (strcmp(str, "voh405_bwbw") == 0) {
216 lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
217 regs_13704_320_240_4bpp,
218 sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
219 logo_bmp_320, sizeof(logo_bmp_320));
221 lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
222 regs_13806_320_240_4bpp,
223 sizeof(regs_13806_320_240_4bpp)/sizeof(regs_13806_320_240_4bpp[0]),
224 logo_bmp_320, sizeof(logo_bmp_320));
225 } else if (strcmp(str, "voh405_bwc") == 0) {
227 lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
228 regs_13704_320_240_4bpp,
229 sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
230 logo_bmp_320, sizeof(logo_bmp_320));
232 lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
233 regs_13806_640_480_16bpp,
234 sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
235 logo_bmp_640, sizeof(logo_bmp_640));
237 printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
242 * Set invert bit in small lcd controller
244 out_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2),
245 in_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2)) | 0x01);
248 * Set default contrast voltage on epson vga controller
250 out_be16(lcd_contrast, 0x4646);
255 out_be16(lcd_backlight, 0xffff);
258 * Enable external I2C bus
260 out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_IIC_ON);
267 * Check Board Identity:
270 int checkboard (void)
273 int i = getenv_f("serial#", str, sizeof(str));
278 puts ("### No HW ID - assuming VOH405");
283 if (getenv_f("bd_type", str, sizeof(str)) != -1) {
284 printf(" (%s)", str);
286 puts(" (Missing bd_type!)");
294 #ifdef CONFIG_IDE_RESET
295 #define FPGA_MODE (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
296 void ide_set_reset(int on)
299 * Assert or deassert CompactFlash Reset Pin
301 if (on) { /* assert RESET */
302 out_be16((void *)FPGA_MODE,
303 in_be16((void *)FPGA_MODE) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
304 } else { /* release RESET */
305 out_be16((void *)FPGA_MODE,
306 in_be16((void *)FPGA_MODE) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
309 #endif /* CONFIG_IDE_RESET */
311 #if defined(CONFIG_RESET_PHY_R)
314 #ifdef CONFIG_LXT971_NO_SLEEP
317 * Disable sleep mode in LXT971
324 #if defined(CONFIG_SYS_EEPROM_WREN)
325 /* Input: <dev_addr> I2C address of EEPROM device to enable.
326 * <state> -1: deliver current state
329 * Returns: -1: wrong device address
330 * 0: dis-/en- able done
331 * 0/1: current state if <state> was -1.
333 int eeprom_write_enable (unsigned dev_addr, int state)
335 if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
340 /* Enable write access, clear bit GPIO0. */
341 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
345 /* Disable write access, set bit GPIO0. */
346 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
350 /* Read current status back. */
351 state = (0 == (in_be32((void*)GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
358 int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
360 int query = argc == 1;
364 /* Query write access state. */
365 state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
367 puts ("Query of write access state failed.\n");
369 printf ("Write access for device 0x%0x is %sabled.\n",
370 CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
374 if ('0' == argv[1][0]) {
375 /* Disable write access. */
376 state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
378 /* Enable write access. */
379 state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
382 puts ("Setup of write access state failed.\n");
389 U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
390 "Enable / disable / query EEPROM write access",
393 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */