2 * (C) Copyright 2001-2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
30 /* ------------------------------------------------------------------------- */
36 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
37 extern void lxt971_no_sleep(void);
39 /* fpga configuration data - gzip compressed and generated by bin2c */
40 const unsigned char fpgadata[] =
46 * include common fpga code (for esd boards)
48 #include "../common/fpga.c"
52 int gunzip(void *, int, unsigned char *, unsigned long *);
55 /* logo bitmap data - gzip compressed and generated by bin2c */
56 unsigned char logo_bmp_320[] =
58 #include "logo_320_240_4bpp.c"
61 unsigned char logo_bmp_640[] =
63 #include "logo_640_480_24bpp.c"
68 * include common lcd code (for esd boards)
70 #include "../common/lcd.c"
72 #include "../common/s1d13704_320_240_4bpp.h"
73 #include "../common/s1d13806_320_240_4bpp.h"
74 #include "../common/s1d13806_640_480_16bpp.h"
77 int board_early_init_f (void)
80 * IRQ 0-15 405GP internally generated; active high; level sensitive
81 * IRQ 16 405GP internally generated; active low; level sensitive
83 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
84 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
85 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
86 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
87 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
88 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
89 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
91 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
92 mtdcr(uicer, 0x00000000); /* disable all ints */
93 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
94 mtdcr(uicpr, 0xFFFFFFB5); /* set int polarities */
95 mtdcr(uictr, 0x10000000); /* set int trigger levels */
96 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
97 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
100 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
102 mtebc (epcr, 0xa8400000); /* ebc always driven */
108 int misc_init_f (void)
110 return 0; /* dummy implementation */
114 int misc_init_r (void)
116 unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
117 unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
118 unsigned short *lcd_contrast =
119 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4);
120 unsigned short *lcd_backlight =
121 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6);
123 ulong len = sizeof(fpgadata);
129 dst = malloc(CFG_FPGA_MAX_SIZE);
130 if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
131 printf ("GUNZIP ERROR - must RESET board to recover\n");
132 do_reset (NULL, 0, 0, NULL);
135 status = fpga_boot(dst, len);
137 printf("\nFPGA: Booting failed ");
139 case ERROR_FPGA_PRG_INIT_LOW:
140 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
142 case ERROR_FPGA_PRG_INIT_HIGH:
143 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
145 case ERROR_FPGA_PRG_DONE:
146 printf("(Timeout: DONE not high after programming FPGA)\n ");
150 /* display infos on fpgaimage */
152 for (i=0; i<4; i++) {
154 printf("FPGA: %s\n", &(dst[index+1]));
159 for (i=20; i>0; i--) {
160 printf("Rebooting in %2d seconds \r",i);
161 for (index=0;index<1000;index++)
165 do_reset(NULL, 0, 0, NULL);
170 /* display infos on fpgaimage */
172 for (i=0; i<4; i++) {
174 printf("%s ", &(dst[index+1]));
182 * Reset FPGA via FPGA_INIT pin
184 out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
185 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~FPGA_INIT); /* reset low */
186 udelay(1000); /* wait 1ms */
187 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | FPGA_INIT); /* reset high */
188 udelay(1000); /* wait 1ms */
191 * Reset external DUARTs
193 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
194 udelay(10); /* wait 10us */
195 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
196 udelay(1000); /* wait 1ms */
199 * Set NAND-FLASH GPIO signals to default
201 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
202 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_NAND_CE);
205 * Setup EEPROM write protection
207 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
208 out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_EEPROM_WP);
211 * Enable interrupts in exar duart mcr[3]
213 out_8(duart0_mcr, 0x08);
214 out_8(duart1_mcr, 0x08);
217 * Init lcd interface and display logo
219 str = getenv("bd_type");
220 if (strcmp(str, "voh405_bw") == 0) {
222 lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
223 regs_13704_320_240_4bpp,
224 sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
225 logo_bmp_320, sizeof(logo_bmp_320));
226 } else if (strcmp(str, "voh405_bwbw") == 0) {
228 lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
229 regs_13704_320_240_4bpp,
230 sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
231 logo_bmp_320, sizeof(logo_bmp_320));
233 lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
234 regs_13806_320_240_4bpp,
235 sizeof(regs_13806_320_240_4bpp)/sizeof(regs_13806_320_240_4bpp[0]),
236 logo_bmp_320, sizeof(logo_bmp_320));
237 } else if (strcmp(str, "voh405_bwc") == 0) {
239 lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
240 regs_13704_320_240_4bpp,
241 sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
242 logo_bmp_320, sizeof(logo_bmp_320));
244 lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
245 regs_13806_640_480_16bpp,
246 sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
247 logo_bmp_640, sizeof(logo_bmp_640));
249 printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
254 * Set invert bit in small lcd controller
256 out_8((unsigned char *)(CFG_LCD_SMALL_REG + 2),
257 in_8((unsigned char *)(CFG_LCD_SMALL_REG + 2)) | 0x01);
260 * Set default contrast voltage on epson vga controller
262 out_be16(lcd_contrast, 0x4646);
267 out_be16(lcd_backlight, 0xffff);
270 * Enable external I2C bus
272 out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_IIC_ON);
279 * Check Board Identity:
282 int checkboard (void)
285 int i = getenv_r ("serial#", str, sizeof(str));
290 puts ("### No HW ID - assuming VOH405");
295 if (getenv_r("bd_type", str, sizeof(str)) != -1) {
296 printf(" (%s)", str);
298 puts(" (Missing bd_type!)");
306 /* ------------------------------------------------------------------------- */
308 phys_size_t initdram (int board_type)
312 mtdcr(memcfga, mem_mb0cf);
313 val = mfdcr(memcfgd);
316 printf("\nmb0cf=%x\n", val); /* test-only */
317 printf("strap=%x\n", mfdcr(strap)); /* test-only */
320 return (4*1024*1024 << ((val & 0x000e0000) >> 17));
323 /* ------------------------------------------------------------------------- */
327 /* TODO: XXX XXX XXX */
328 printf ("test: 16 MB - ok\n");
333 /* ------------------------------------------------------------------------- */
335 #ifdef CONFIG_IDE_RESET
336 void ide_set_reset(int on)
338 volatile unsigned short *fpga_mode =
339 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
342 * Assert or deassert CompactFlash Reset Pin
344 if (on) { /* assert RESET */
345 *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
346 } else { /* release RESET */
347 *fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
350 #endif /* CONFIG_IDE_RESET */
352 #if defined(CONFIG_RESET_PHY_R)
355 #ifdef CONFIG_LXT971_NO_SLEEP
358 * Disable sleep mode in LXT971
365 #if defined(CFG_EEPROM_WREN)
366 /* Input: <dev_addr> I2C address of EEPROM device to enable.
367 * <state> -1: deliver current state
370 * Returns: -1: wrong device address
371 * 0: dis-/en- able done
372 * 0/1: current state if <state> was -1.
374 int eeprom_write_enable (unsigned dev_addr, int state)
376 if (CFG_I2C_EEPROM_ADDR != dev_addr) {
381 /* Enable write access, clear bit GPIO0. */
382 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP);
386 /* Disable write access, set bit GPIO0. */
387 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
391 /* Read current status back. */
392 state = (0 == (in_be32((void*)GPIO0_OR) & CFG_EEPROM_WP));
399 int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
401 int query = argc == 1;
405 /* Query write access state. */
406 state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
408 puts ("Query of write access state failed.\n");
410 printf ("Write access for device 0x%0x is %sabled.\n",
411 CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
415 if ('0' == argv[1][0]) {
416 /* Disable write access. */
417 state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
419 /* Enable write access. */
420 state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
423 puts ("Setup of write access state failed.\n");
430 U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
431 "eepwren - Enable / disable / query EEPROM write access\n",
433 #endif /* #if defined(CFG_EEPROM_WREN) */