2 * (C) Copyright 2007-2008
3 * Matthias Fuchs, esd Gmbh, matthias.fuchs@esd-electronics.com.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/cache.h>
28 #include <asm/processor.h>
33 int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
34 uchar *buffer, unsigned cnt);
35 int eeprom_write_enable(unsigned dev_addr, int state);
37 DECLARE_GLOBAL_DATA_PTR;
39 #if defined(CONFIG_CMD_BSP)
41 static int got_fifoirq;
44 int fpga_interrupt(u32 arg)
46 pmc440_fpga_t *fpga = (pmc440_fpga_t *)arg;
47 int rc = -1; /* not for us */
48 u32 status = FPGA_IN32(&fpga->status);
50 /* check for interrupt from fifo module */
51 if (status & STATUS_FIFO_ISF) {
52 /* disable this int source */
53 FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
55 got_fifoirq = 1; /* trigger backend */
58 if (status & STATUS_HOST_ISF) {
59 FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
67 int do_waithci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
69 pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
73 FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
74 FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
76 irq_install_handler(IRQ0_FPGA,
77 (interrupt_handler_t *)fpga_interrupt,
80 FPGA_SETBITS(&fpga->ctrla, CTRL_HOST_IE);
83 /* Abort if ctrl-c was pressed */
90 printf("Got interrupt!\n");
92 FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
93 irq_free_handler(IRQ0_FPGA);
97 waithci, 1, 1, do_waithci,
98 "waithci - Wait for host control interrupt\n",
102 void dump_fifo(pmc440_fpga_t *fpga, int f, int *n)
106 while (!((ctrl = FPGA_IN32(&fpga->fifo[f].ctrl)) & FIFO_EMPTY)) {
107 printf("%5d %d %3d %08x",
108 (*n)++, f, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
109 FPGA_IN32(&fpga->fifo[f].data));
110 if (ctrl & FIFO_OVERFLOW) {
111 printf(" OVERFLOW\n");
112 FPGA_CLRBITS(&fpga->fifo[f].ctrl, FIFO_OVERFLOW);
118 int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
120 pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
124 char str[] = "\\|/-";
131 /* print all fifos status information */
132 printf("fifo level status\n");
133 printf("______________________________\n");
134 for (i=0; i<FIFO_COUNT; i++) {
135 ctrl = FPGA_IN32(&fpga->fifo[i].ctrl);
136 printf(" %d %3d %s%s%s %s\n",
137 i, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
138 ctrl & FIFO_FULL ? "FULL " : "",
139 ctrl & FIFO_EMPTY ? "EMPTY " : "",
140 ctrl & (FIFO_FULL|FIFO_EMPTY) ? "" : "NOT EMPTY",
141 ctrl & FIFO_OVERFLOW ? "OVERFLOW" : "");
146 /* completely read out fifo 'n' */
147 if (!strcmp(argv[1],"read")) {
148 printf(" # fifo level data\n");
149 printf("______________________________\n");
151 for (i=0; i<FIFO_COUNT; i++)
152 dump_fifo(fpga, i, &n);
154 } else if (!strcmp(argv[1],"wait")) {
157 irq_install_handler(IRQ0_FPGA,
158 (interrupt_handler_t *)fpga_interrupt,
161 printf(" # fifo level data\n");
162 printf("______________________________\n");
164 /* enable all fifo interrupts */
165 FPGA_OUT32(&fpga->hostctrl,
166 HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG);
167 for (i=0; i<FIFO_COUNT; i++) {
168 /* enable interrupts from all fifos */
169 FPGA_SETBITS(&fpga->fifo[i].ctrl, FIFO_IE);
174 while (!got_fifoirq) {
176 if (!(count % 100)) {
178 putc(0x08); /* backspace */
179 putc(str[count2 % 4]);
182 /* Abort if ctrl-c was pressed */
183 if ((abort = ctrlc())) {
192 /* simple fifo backend */
194 for (i=0; i<FIFO_COUNT; i++)
195 dump_fifo(fpga, i, &n);
198 /* unmask global fifo irq */
199 FPGA_OUT32(&fpga->hostctrl,
200 HOSTCTRL_FIFOIE_GATE |
201 HOSTCTRL_FIFOIE_FLAG);
205 /* disable all fifo interrupts */
206 FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
207 for (i=0; i<FIFO_COUNT; i++)
208 FPGA_CLRBITS(&fpga->fifo[i].ctrl, FIFO_IE);
210 irq_free_handler(IRQ0_FPGA);
213 printf("Usage:\nfifo %s\n", cmdtp->help);
220 if (!strcmp(argv[1],"write")) {
221 /* get fifo number or fifo address */
222 f = simple_strtoul(argv[2], NULL, 16);
225 data = simple_strtoul(argv[3], NULL, 16);
227 /* get optional count parameter */
230 n = (int)simple_strtoul(argv[4], NULL, 10);
232 if (f < FIFO_COUNT) {
233 printf("writing %d x %08x to fifo %d\n",
236 FPGA_OUT32(&fpga->fifo[f].data, data);
238 printf("writing %d x %08x to fifo port at "
245 printf("Usage:\nfifo %s\n", cmdtp->help);
251 printf("Usage:\nfifo %s\n", cmdtp->help);
258 "fifo - Fifo module operations\n",
260 "fifo write fifo(0..3) data [cnt=1]\n"
261 "fifo write address(>=4) data [cnt=1]\n"
262 " - without arguments: print all fifo's status\n"
263 " - with 'wait' argument: interrupt driven read from all fifos\n"
264 " - with 'read' argument: read current contents from all fifos\n"
265 " - with 'write' argument: write 'data' 'cnt' times to "
266 "'fifo' or 'address'\n"
269 int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
276 printf("Usage:\nsbe %s\n", cmdtp->help);
281 if (!strcmp(argv[1], "400")) {
282 /* PLB=133MHz, PLB/PCI=3 */
283 printf("Bootstrapping for 400MHz\n");
288 } else if (!strcmp(argv[1], "533")) {
289 /* PLB=133MHz, PLB/PCI=3 */
290 printf("Bootstrapping for 533MHz\n");
295 } else if (!strcmp(argv[1], "667")) {
296 /* PLB=133MHz, PLB/PCI=3 */
297 printf("Bootstrapping for 667MHz\n");
303 printf("Usage:\nsbe %s\n", cmdtp->help);
312 else if (argv[2][0]=='0')
319 delay = simple_strtoul(argv[3], NULL, 10);
325 printf("Writing boot EEPROM ...\n");
326 if (bootstrap_eeprom_write(CFG_I2C_BOOT_EEPROM_ADDR,
327 0, (uchar*)sdsdp, count) != 0)
328 printf("bootstrap_eeprom_write failed\n");
330 printf("done (dump via 'i2c md 52 0.1 14')\n");
335 sbe, 4, 0, do_setup_bootstrap_eeprom,
336 "sbe - setup bootstrap eeprom\n",
337 "<cpufreq:400|533|667> [<console-uart:0|1> [<bringup delay (0..20s)>]]"
340 #if defined(CONFIG_PRAM)
341 #include <environment.h>
342 extern env_t *env_ptr;
344 int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
352 memsize = gd->bd->bi_memsize;
356 pram = simple_strtoul(v, NULL, 10);
358 printf("Error: pram undefined. Please define pram in KiB\n");
362 param = memsize - (pram << 10);
363 printf("PARAM: @%08x\n", param);
365 memset((void*)param, 0, (pram << 10));
366 env_base = memsize - 4096 - ((CFG_ENV_SIZE + 4096) & ~(4096-1));
367 memcpy((void*)env_base, env_ptr, CFG_ENV_SIZE);
369 lptr = (ulong*)memsize;
370 *(--lptr) = CFG_ENV_SIZE;
371 *(--lptr) = memsize - env_base;
372 *(--lptr) = crc32(0, (void*)(memsize - 0x08), 0x08);
375 /* make sure data can be accessed through PCI */
376 flush_dcache_range(param, param + (pram << 10) - 1);
380 painit, 1, 1, do_painit,
381 "painit - prepare PciAccess system\n",
384 #endif /* CONFIG_PRAM */
386 int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
389 if (argv[1][0] == '0') {
391 printf("self-reset# asserted\n");
392 out_be32((void*)GPIO0_TCR,
393 in_be32((void*)GPIO0_TCR) | GPIO0_SELF_RST);
396 printf("self-reset# deasserted\n");
397 out_be32((void*)GPIO0_TCR,
398 in_be32((void*)GPIO0_TCR) & ~GPIO0_SELF_RST);
401 printf("self-reset# is %s\n",
402 in_be32((void*)GPIO0_TCR) & GPIO0_SELF_RST ?
403 "active" : "inactive");
409 selfreset, 2, 1, do_selfreset,
410 "selfreset- assert self-reset# signal\n",
414 int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
416 pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
418 /* requiers bootet FPGA and PLD_IOEN_N active */
419 if (in_be32((void*)GPIO1_OR) & GPIO1_IOEN_N) {
420 printf("Error: resetout requires a bootet FPGA\n");
425 if (argv[1][0] == '0') {
427 printf("PMC-RESETOUT# asserted\n");
428 FPGA_OUT32(&fpga->hostctrl,
429 HOSTCTRL_PMCRSTOUT_GATE);
432 printf("PMC-RESETOUT# deasserted\n");
433 FPGA_OUT32(&fpga->hostctrl,
434 HOSTCTRL_PMCRSTOUT_GATE |
435 HOSTCTRL_PMCRSTOUT_FLAG);
438 printf("PMC-RESETOUT# is %s\n",
439 FPGA_IN32(&fpga->hostctrl) & HOSTCTRL_PMCRSTOUT_FLAG ?
440 "inactive" : "active");
446 resetout, 2, 1, do_resetout,
447 "resetout - assert PMC-RESETOUT# signal\n",
451 int do_inta(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
454 printf("This command is only supported in non-monarch mode\n");
459 if (argv[1][0] == '0') {
461 printf("inta# asserted\n");
462 out_be32((void*)GPIO1_TCR,
463 in_be32((void*)GPIO1_TCR) | GPIO1_INTA_FAKE);
466 printf("inta# deasserted\n");
467 out_be32((void*)GPIO1_TCR,
468 in_be32((void*)GPIO1_TCR) & ~GPIO1_INTA_FAKE);
471 printf("inta# is %s\n",
472 in_be32((void*)GPIO1_TCR) & GPIO1_INTA_FAKE ?
473 "active" : "inactive");
479 "inta - Assert/Deassert or query INTA# state in non-monarch mode\n",
484 int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
489 pciaddr = simple_strtoul(argv[1], NULL, 16);
491 pciaddr &= 0xf0000000;
493 /* map PCI address at 0xc0000000 in PLB space */
495 /* PMM1 Mask/Attribute - disabled b4 setting */
496 out32r(PCIX0_PMM1MA, 0x00000000);
497 /* PMM1 Local Address */
498 out32r(PCIX0_PMM1LA, 0xc0000000);
499 /* PMM1 PCI Low Address */
500 out32r(PCIX0_PMM1PCILA, pciaddr);
501 /* PMM1 PCI High Address */
502 out32r(PCIX0_PMM1PCIHA, 0x00000000);
503 /* 256MB + No prefetching, and enable region */
504 out32r(PCIX0_PMM1MA, 0xf0000001);
506 printf("Usage:\npmm %s\n", cmdtp->help);
512 "pmm - Setup pmm[1] registers\n",
513 "<pciaddr> (pciaddr will be aligned to 256MB)\n"
516 #if defined(CFG_EEPROM_WREN)
517 int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
519 int query = argc == 1;
523 /* Query write access state. */
524 state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, -1);
526 puts("Query of write access state failed.\n");
528 printf("Write access for device 0x%0x is %sabled.\n",
529 CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
533 if ('0' == argv[1][0]) {
534 /* Disable write access. */
535 state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 0);
537 /* Enable write access. */
538 state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 1);
541 puts("Setup of write access state failed.\n");
547 U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
548 "eepwren - Enable / disable / query EEPROM write access\n",
550 #endif /* #if defined(CFG_EEPROM_WREN) */
552 #endif /* CONFIG_CMD_BSP */