3 * Matthias Fuchs, esd Gmbh, matthias.fuchs@esd-electronics.com.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/cache.h>
29 #include <asm/processor.h>
34 int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
35 int eeprom_write_enable(unsigned dev_addr, int state);
37 DECLARE_GLOBAL_DATA_PTR;
39 #if defined(CONFIG_CMD_BSP)
41 static int got_fifoirq;
44 int fpga_interrupt(u32 arg)
46 pmc440_fpga_t *fpga = (pmc440_fpga_t *)arg;
47 int rc = -1; /* not for us */
48 u32 status = FPGA_IN32(&fpga->status);
50 /* check for interrupt from fifo module */
51 if (status & STATUS_FIFO_ISF) {
52 /* disable this int source */
53 FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
55 got_fifoirq = 1; /* trigger backend */
58 if (status & STATUS_HOST_ISF) {
59 FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
68 int do_waithci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
70 pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
74 FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
75 FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
77 irq_install_handler(IRQ0_FPGA,
78 (interrupt_handler_t *)fpga_interrupt,
81 FPGA_SETBITS(&fpga->ctrla, CTRL_HOST_IE);
84 /* Abort if ctrl-c was pressed */
91 printf("Got interrupt!\n");
93 FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
94 irq_free_handler(IRQ0_FPGA);
98 waithci, 1, 1, do_waithci,
99 "waithci - Wait for host control interrupt\n",
104 void dump_fifo(pmc440_fpga_t *fpga, int f, int *n)
108 while (!((ctrl = FPGA_IN32(&fpga->fifo[f].ctrl)) & FIFO_EMPTY)) {
109 printf("%5d %d %3d %08x",
110 (*n)++, f, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
111 FPGA_IN32(&fpga->fifo[f].data));
112 if (ctrl & FIFO_OVERFLOW) {
113 printf(" OVERFLOW\n");
114 FPGA_CLRBITS(&fpga->fifo[f].ctrl, FIFO_OVERFLOW);
121 int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
123 pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
127 char str[] = "\\|/-";
134 /* print all fifos status information */
135 printf("fifo level status\n");
136 printf("______________________________\n");
137 for (i=0; i<FIFO_COUNT; i++) {
138 ctrl = FPGA_IN32(&fpga->fifo[i].ctrl);
139 printf(" %d %3d %s%s%s %s\n",
140 i, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
141 ctrl & FIFO_FULL ? "FULL " : "",
142 ctrl & FIFO_EMPTY ? "EMPTY " : "",
143 ctrl & (FIFO_FULL|FIFO_EMPTY) ? "" : "NOT EMPTY",
144 ctrl & FIFO_OVERFLOW ? "OVERFLOW" : "");
149 /* completely read out fifo 'n' */
150 if (!strcmp(argv[1],"read")) {
151 printf(" # fifo level data\n");
152 printf("______________________________\n");
154 for (i=0; i<FIFO_COUNT; i++)
155 dump_fifo(fpga, i, &n);
157 } else if (!strcmp(argv[1],"wait")) {
160 irq_install_handler(IRQ0_FPGA,
161 (interrupt_handler_t *)fpga_interrupt,
164 printf(" # fifo level data\n");
165 printf("______________________________\n");
167 /* enable all fifo interrupts */
168 FPGA_OUT32(&fpga->hostctrl,
169 HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG);
170 for (i=0; i<FIFO_COUNT; i++) {
171 /* enable interrupts from all fifos */
172 FPGA_SETBITS(&fpga->fifo[i].ctrl, FIFO_IE);
177 while (!got_fifoirq) {
179 if (!(count % 100)) {
181 putc(0x08); /* backspace */
182 putc(str[count2 % 4]);
185 /* Abort if ctrl-c was pressed */
186 if ((abort = ctrlc())) {
195 /* simple fifo backend */
197 for (i=0; i<FIFO_COUNT; i++)
198 dump_fifo(fpga, i, &n);
201 /* unmask global fifo irq */
202 FPGA_OUT32(&fpga->hostctrl,
203 HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG);
207 /* disable all fifo interrupts */
208 FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
209 for (i=0; i<FIFO_COUNT; i++)
210 FPGA_CLRBITS(&fpga->fifo[i].ctrl, FIFO_IE);
212 irq_free_handler(IRQ0_FPGA);
215 printf("Usage:\nfifo %s\n", cmdtp->help);
222 if (!strcmp(argv[1],"write")) {
223 /* get fifo number or fifo address */
224 f = simple_strtoul(argv[2], NULL, 16);
227 data = simple_strtoul(argv[3], NULL, 16);
229 /* get optional count parameter */
232 n = (int)simple_strtoul(argv[4], NULL, 10);
234 if (f < FIFO_COUNT) {
235 printf("writing %d x %08x to fifo %d\n",
238 FPGA_OUT32(&fpga->fifo[f].data, data);
240 printf("writing %d x %08x to fifo port at address %08x\n",
246 printf("Usage:\nfifo %s\n", cmdtp->help);
252 printf("Usage:\nfifo %s\n", cmdtp->help);
259 "fifo - Fifo module operations\n",
261 "fifo write fifo(0..3) data [cnt=1]\n"
262 "fifo write address(>=4) data [cnt=1]\n"
263 " - without arguments: print all fifo's status\n"
264 " - with 'wait' argument: interrupt driven read from all fifos\n"
265 " - with 'read' argument: read current contents from all fifos\n"
266 " - with 'write' argument: write 'data' 'cnt' times to 'fifo' or 'address'\n"
270 int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
277 printf("Usage:\nsbe %s\n", cmdtp->help);
282 if (!strcmp(argv[1], "400")) {
283 /* PLB=133MHz, PLB/PCI=3 */
284 printf("Bootstrapping for 400MHz\n");
289 } else if (!strcmp(argv[1], "533")) {
290 /* PLB=133MHz, PLB/PCI=3 */
291 printf("Bootstrapping for 533MHz\n");
296 } else if (!strcmp(argv[1], "667")) {
297 /* PLB=133MHz, PLB/PCI=4 */
298 printf("Bootstrapping for 667MHz\n");
303 } else if (!strcmp(argv[1], "test")) {
304 /* TODO: this will replace the 667 MHz config above.
305 * But it needs some more testing on a real 667 MHz CPU.
307 printf("Bootstrapping for test (667MHz PLB=133PLB PLB/PCI=3)\n");
313 printf("Usage:\nsbe %s\n", cmdtp->help);
322 else if (argv[2][0]=='0')
329 delay = simple_strtoul(argv[3], NULL, 10);
335 printf("Writing boot EEPROM ...\n");
336 if (bootstrap_eeprom_write(CFG_I2C_BOOT_EEPROM_ADDR,
337 0, (uchar*)sdsdp, count) != 0)
338 printf("bootstrap_eeprom_write failed\n");
340 printf("done (dump via 'i2c md 52 0.1 14')\n");
345 sbe, 4, 0, do_setup_bootstrap_eeprom,
346 "sbe - setup bootstrap eeprom\n",
347 "<cpufreq:400|533|667> [<console-uart:0|1> [<bringup delay (0..20s)>]]"
351 #if defined(CONFIG_PRAM)
352 #include <environment.h>
353 extern env_t *env_ptr;
355 int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
363 memsize = gd->bd->bi_memsize;
367 pram = simple_strtoul(v, NULL, 10);
369 printf("Error: pram undefined. Please define pram in KiB\n");
373 param = memsize - (pram << 10);
374 printf("PARAM: @%08x\n", param);
376 memset((void*)param, 0, (pram << 10));
377 env_base = memsize - 4096 - ((CFG_ENV_SIZE + 4096) & ~(4096-1));
378 memcpy((void*)env_base, env_ptr, CFG_ENV_SIZE);
380 lptr = (ulong*)memsize;
381 *(--lptr) = CFG_ENV_SIZE;
382 *(--lptr) = memsize - env_base;
383 *(--lptr) = crc32(0, (void*)(memsize - 0x08), 0x08);
386 /* make sure data can be accessed through PCI */
387 flush_dcache_range(param, param + (pram << 10) - 1);
391 painit, 1, 1, do_painit,
392 "painit - prepare PciAccess system\n",
395 #endif /* CONFIG_PRAM */
398 int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
401 if (argv[1][0] == '0') {
403 printf("self-reset# asserted\n");
404 out_be32((void*)GPIO0_TCR,
405 in_be32((void*)GPIO0_TCR) | GPIO0_SELF_RST);
408 printf("self-reset# deasserted\n");
409 out_be32((void*)GPIO0_TCR,
410 in_be32((void*)GPIO0_TCR) & ~GPIO0_SELF_RST);
413 printf("self-reset# is %s\n",
414 in_be32((void*)GPIO0_TCR) & GPIO0_SELF_RST ?
415 "active" : "inactive");
421 selfreset, 2, 1, do_selfreset,
422 "selfreset- assert self-reset# signal\n",
427 int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
429 pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
431 /* requiers bootet FPGA and PLD_IOEN_N active */
432 if (in_be32((void*)GPIO1_OR) & GPIO1_IOEN_N) {
433 printf("Error: resetout requires a bootet FPGA\n");
438 if (argv[1][0] == '0') {
440 printf("PMC-RESETOUT# asserted\n");
441 FPGA_OUT32(&fpga->hostctrl,
442 HOSTCTRL_PMCRSTOUT_GATE);
445 printf("PMC-RESETOUT# deasserted\n");
446 FPGA_OUT32(&fpga->hostctrl,
447 HOSTCTRL_PMCRSTOUT_GATE | HOSTCTRL_PMCRSTOUT_FLAG);
450 printf("PMC-RESETOUT# is %s\n",
451 FPGA_IN32(&fpga->hostctrl) & HOSTCTRL_PMCRSTOUT_FLAG ?
452 "inactive" : "active");
458 resetout, 2, 1, do_resetout,
459 "resetout - assert PMC-RESETOUT# signal\n",
464 int do_inta(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
467 printf("This command is only supported in non-monarch mode\n");
472 if (argv[1][0] == '0') {
474 printf("inta# asserted\n");
475 out_be32((void*)GPIO1_TCR,
476 in_be32((void*)GPIO1_TCR) | GPIO1_INTA_FAKE);
479 printf("inta# deasserted\n");
480 out_be32((void*)GPIO1_TCR,
481 in_be32((void*)GPIO1_TCR) & ~GPIO1_INTA_FAKE);
484 printf("inta# is %s\n", in_be32((void*)GPIO1_TCR) & GPIO1_INTA_FAKE ? "active" : "inactive");
490 "inta - Assert/Deassert or query INTA# state in non-monarch mode\n",
496 int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
501 pciaddr = simple_strtoul(argv[1], NULL, 16);
503 pciaddr &= 0xf0000000;
505 /* map PCI address at 0xc0000000 in PLB space */
506 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM1 Mask/Attribute - disabled b4 setting */
507 out32r(PCIX0_PMM1LA, 0xc0000000); /* PMM1 Local Address */
508 out32r(PCIX0_PMM1PCILA, pciaddr); /* PMM1 PCI Low Address */
509 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM1 PCI High Address */
510 out32r(PCIX0_PMM1MA, 0xf0000001); /* 256MB + No prefetching, and enable region */
512 printf("Usage:\npmm %s\n", cmdtp->help);
518 "pmm - Setup pmm[1] registers\n",
519 "<pciaddr> (pciaddr will be aligned to 256MB)\n"
522 #if defined(CFG_EEPROM_WREN)
523 int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
525 int query = argc == 1;
529 /* Query write access state. */
530 state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, -1);
532 puts("Query of write access state failed.\n");
534 printf("Write access for device 0x%0x is %sabled.\n",
535 CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
539 if ('0' == argv[1][0]) {
540 /* Disable write access. */
541 state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 0);
543 /* Enable write access. */
544 state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 1);
547 puts("Setup of write access state failed.\n");
553 U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
554 "eepwren - Enable / disable / query EEPROM write access\n",
556 #endif /* #if defined(CFG_EEPROM_WREN) */
558 #endif /* CONFIG_CMD_BSP */