2 * (C) Copyright 2010-2011
3 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
4 * esd electronic system design gmbh <www.esd.eu>
6 * (C) Copyright 2007-2008
7 * Stelian Pop <stelian@popies.net>
8 * Lead Tech Design <www.leadtechdesign.com>
10 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/at91sam9_smc.h>
17 #include <asm/arch/at91_common.h>
18 #include <asm/arch/at91_pmc.h>
19 #include <asm/arch/at91_rstc.h>
20 #include <asm/arch/at91_matrix.h>
21 #include <asm/arch/at91_pio.h>
22 #include <asm/arch/clk.h>
25 # include <atmel_lcdc.h>
27 # ifdef CONFIG_LCD_INFO
33 DECLARE_GLOBAL_DATA_PTR;
36 * Miscelaneous platform dependent initialisations
39 static int hw_rev = -1; /* hardware revision */
46 hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
47 hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
48 hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
49 hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
57 #ifdef CONFIG_CMD_NAND
58 static void otc570_nand_hw_init(void)
61 at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
62 at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
65 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
66 writel(csa, &matrix->csa[0]);
68 /* Configure SMC CS3 for NAND/SmartMedia */
69 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
70 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2),
73 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
74 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
77 writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
79 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
80 AT91_SMC_MODE_EXNW_DISABLE |
82 AT91_SMC_MODE_TDF_CYCLE(12),
85 /* Configure RDY/BSY */
86 gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
88 /* Enable NandFlash */
89 gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
91 #endif /* CONFIG_CMD_NAND */
94 static void otc570_macb_hw_init(void)
96 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
98 writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
104 * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
105 * controller debugging
106 * The ET1100 is located at physical address 0x70000000
107 * Its process memory is located at physical address 0x70001000
109 static void otc570_ethercat_hw_init(void)
111 at91_smc_t *smc1 = (at91_smc_t *) ATMEL_BASE_SMC1;
113 /* Configure SMC EBI1_CS0 for EtherCAT */
114 writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
115 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
117 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
118 AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
120 writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
123 * Configure behavior at external wait signal, byte-select mode, 16 bit
124 * data bus width, none data float wait states and TDF optimization
126 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
127 AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
128 AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
130 /* Configure RDY/BSY */
131 at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */
135 /* Number of columns and rows, pixel clock in Hz and hsync/vsync polarity */
136 vidinfo_t panel_info = {
140 .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
141 ATMEL_LCDC_INVFRAME_INVERTED,
143 .vl_bpix = LCD_BPP,/* Bits per pixel, 0 = 1bit, 3 = 8bit */
144 .vl_tft = 1, /* 0 = passive, 1 = TFT */
145 .vl_vsync_len = 1, /* Length of vertical sync in NOL */
146 .vl_upper_margin = 35, /* Idle lines at the frame start */
147 .vl_lower_margin = 5, /* Idle lines at the end of the frame */
148 .vl_hsync_len = 5, /* Width of the LCDHSYNC pulse */
149 .vl_left_margin = 112, /* Idle cycles at the line beginning */
150 .vl_right_margin = 1, /* Idle cycles at the end of the line */
152 .mmio = ATMEL_BASE_LCDC,
155 void lcd_enable(void)
157 at91_set_pio_value(AT91_PIO_PORTA, 30, 0); /* power up */
160 void lcd_disable(void)
162 at91_set_pio_value(AT91_PIO_PORTA, 30, 1); /* power down */
165 static void otc570_lcd_hw_init(void)
167 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
169 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */
170 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
171 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
172 at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
173 at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
174 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
175 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
176 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
177 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
178 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
179 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
180 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
181 at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
182 at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
183 at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
184 at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
185 at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
186 at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
187 at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
188 at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
189 at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
190 at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
191 at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
192 at91_set_pio_output(AT91_PIO_PORTA, 30, 1); /* PCI */
194 writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
197 #ifdef CONFIG_LCD_INFO
198 void lcd_show_board_info(void)
200 ulong dram_size, nand_size;
205 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
206 dram_size += gd->bd->bi_dram[i].size;
208 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
209 nand_size += nand_info[i].size;
211 lcd_printf("\n%s\n", U_BOOT_VERSION);
212 lcd_printf("CPU at %s MHz\n", strmhz(temp, get_cpu_clk_rate()));
213 lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
216 lcd_printf(" Board : esd ARM9 HMI Panel - OTC570\n");
217 lcd_printf(" Hardware-revision: 1.%d\n", get_hw_rev());
218 lcd_printf(" Mach-type : %lu\n", gd->bd->bi_arch_number);
220 #endif /* CONFIG_LCD_INFO */
221 #endif /* CONFIG_LCD */
225 gd->ram_size = get_ram_size(
226 (void *)CONFIG_SYS_SDRAM_BASE,
227 CONFIG_SYS_SDRAM_SIZE);
231 int board_eth_init(bd_t *bis)
235 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
244 puts("Board : esd ARM9 HMI Panel - OTC570");
245 if (getenv_f("serial#", str, sizeof(str)) > 0) {
250 printf("Hardware-revision: 1.%d\n", get_hw_rev());
251 printf("Mach-type : %lu\n", gd->bd->bi_arch_number);
255 #ifdef CONFIG_SERIAL_TAG
256 void get_board_serial(struct tag_serialnr *serialnr)
260 char *serial = getenv("serial#");
262 str = strchr(serial, '_');
263 if (str && (strlen(str) >= 4)) {
264 serialnr->high = (*(str + 1) << 8) | *(str + 2);
265 serialnr->low = simple_strtoul(str + 3, NULL, 16);
274 #ifdef CONFIG_REVISION_TAG
275 u32 get_board_rev(void)
277 return hw_rev | 0x100;
281 #ifdef CONFIG_MISC_INIT_R
282 int misc_init_r(void)
285 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
287 at91_set_pio_output(AT91_PIO_PORTA, 29, 1);
288 at91_set_a_periph(AT91_PIO_PORTA, 26, 1); /* TXD0 */
289 at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* RXD0 */
290 writel(1 << ATMEL_ID_USART0, &pmc->pcer);
291 /* Set USART_MODE = 1 (RS485) */
292 writel(1, 0xFFF8C004);
296 if (getenv_f("usart0", str, sizeof(str)) == -1) {
297 printf("No entry - assuming 1-wire\n");
298 /* CTS pin, works as mode select pin (0 = 1-wire; 1 = RS485) */
299 at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
301 if (strcmp(str, "1-wire") == 0) {
303 at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
304 } else if (strcmp(str, "rs485") == 0) {
306 at91_set_pio_output(AT91_PIO_PORTA, 29, 1);
308 printf("Wrong entry - assuming 1-wire ");
309 printf("(valid values are '1-wire' or 'rs485')\n");
310 at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
314 printf("Display memory address: 0x%08lX\n", gd->fb_base);
319 #endif /* CONFIG_MISC_INIT_R */
321 int board_early_init_f(void)
323 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
325 /* enable all clocks */
326 writel((1 << ATMEL_ID_PIOA) |
327 (1 << ATMEL_ID_PIOB) |
328 (1 << ATMEL_ID_PIOCDE) |
329 (1 << ATMEL_ID_TWI) |
330 (1 << ATMEL_ID_SPI0) |
332 (1 << ATMEL_ID_LCDC) |
337 at91_seriald_hw_init();
339 /* arch number of OTC570-Board */
340 gd->bd->bi_arch_number = MACH_TYPE_OTC570;
347 /* initialize ET1100 Controller */
348 otc570_ethercat_hw_init();
350 /* adress of boot parameters */
351 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
353 #ifdef CONFIG_CMD_NAND
354 otc570_nand_hw_init();
356 #ifdef CONFIG_HAS_DATAFLASH
357 at91_spi0_hw_init(1 << 0);
360 otc570_macb_hw_init();
362 #ifdef CONFIG_AT91_CAN
365 #ifdef CONFIG_USB_OHCI_NEW
369 otc570_lcd_hw_init();