2 * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
3 * (C) Copyright 2009 Dave Srl www.dave.eu
4 * (C) Copyright 2009 Stefan Roese <sr@denx.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/bitops.h>
30 #include <asm/processor.h>
31 #include <asm/mpc512x.h>
32 #include <fdt_support.h>
34 DECLARE_GLOBAL_DATA_PTR;
36 int eeprom_write_enable(unsigned dev_addr, int state)
38 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
40 if (dev_addr != CONFIG_SYS_I2C_EEPROM_ADDR)
44 setbits_be32(&im->gpio.gpdat, 0x00100000);
46 clrbits_be32(&im->gpio.gpdat, 0x00100000);
51 int board_early_init_f(void)
53 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
57 * Initialize Local Window for boot access
59 out_be32(&im->sysconf.lpbaw,
60 CSAW_START(0xffb00000) | CSAW_STOP(0xffb00000, 0x00010000));
61 sync_law(&im->sysconf.lpbaw);
64 * Configure MSCAN clocks
67 out_be32(&im->clk.msccr[i], 0x00300000);
68 out_be32(&im->clk.msccr[i], 0x00310000);
74 clrbits_be32(&im->gpio.gpodr, 0x000000e0);
75 clrbits_be32(&im->gpio.gpdir, 0x00ef0000);
76 setbits_be32(&im->gpio.gpdir, 0x001000e0);
77 setbits_be32(&im->gpio.gpdat, 0x00100000);
82 phys_size_t initdram(int board_type)
84 return get_ram_size(0, fixed_sdram(NULL, NULL, 0));
89 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
93 * Optimize access to profibus chip (VPC3) on the local bus
97 * Select 1:1 for LPC_DIV
99 val = in_be32(&im->clk.scfr[0]) & ~SCFR1_LPC_DIV_MASK;
100 out_be32(&im->clk.scfr[0], val | (0x1 << SCFR1_LPC_DIV_SHIFT));
103 * Configure LPC Chips Select Deadcycle Control Register
104 * CS0 - device can drive data 2 clock cycle(s) after CS deassertion
105 * CS1 - device can drive data 1 clock cycle(s) after CS deassertion
107 clrbits_be32(&im->lpc.cs_dccr, 0x000000ff);
108 setbits_be32(&im->lpc.cs_dccr, (0x00 << 4) | (0x01 << 0));
111 * Configure LPC Chips Select Holdcycle Control Register
112 * CS0 - data is valid 2 clock cycle(s) after CS deassertion
113 * CS1 - data is valid 1 clock cycle(s) after CS deassertion
115 clrbits_be32(&im->lpc.cs_hccr, 0x000000ff);
116 setbits_be32(&im->lpc.cs_hccr, (0x00 << 4) | (0x01 << 0));
121 static iopin_t ioregs_init[] = {
122 /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
124 offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
125 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
126 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
128 /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
130 offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
131 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
132 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
134 /* FUNC1=SELECT LPC_CS1 */
136 offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
137 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
138 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
140 /* FUNC3=SELECT PSC5_2 */
142 offsetof(struct ioctrl512x, io_control_psc5_2), 1, 0,
143 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
144 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
146 /* FUNC3=SELECT PSC5_3 */
148 offsetof(struct ioctrl512x, io_control_psc5_3), 1, 0,
149 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
150 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
152 /* FUNC3=SELECT PSC7_3 */
154 offsetof(struct ioctrl512x, io_control_psc7_3), 1, 0,
155 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
156 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
158 /* FUNC3=SELECT PSC9_0 */
160 offsetof(struct ioctrl512x, io_control_psc9_0), 3, 0,
161 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
162 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
164 /* FUNC3=SELECT PSC10_0 */
166 offsetof(struct ioctrl512x, io_control_psc10_0), 3, 0,
167 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
168 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
170 /* FUNC3=SELECT PSC10_3 */
172 offsetof(struct ioctrl512x, io_control_psc10_3), 1, 0,
173 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
174 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
176 /* FUNC3=SELECT PSC11_0 */
178 offsetof(struct ioctrl512x, io_control_psc11_0), 4, 0,
179 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
180 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
182 /* FUNC0=SELECT IRQ0 */
184 offsetof(struct ioctrl512x, io_control_irq0), 4, 0,
185 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
186 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
190 static iopin_t rev2_silicon_pci_ioregs_init[] = {
191 /* FUNC0=PCI Sets next 54 to PCI pads */
193 offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
194 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
200 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
203 puts("Board: MECP_5123\n");
206 * Initialize function mux & slew rate IO inter alia on IO
209 iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
211 spridr = in_be32(&im->sysconf.spridr);
212 if (SVR_MJREV(spridr) >= 2)
213 iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
218 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
219 void ft_board_setup(void *blob, bd_t *bd)
221 ft_cpu_setup(blob, bd);
223 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */