2 * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
3 * (C) Copyright 2009 Dave Srl www.dave.eu
4 * (C) Copyright 2009 Stefan Roese <sr@denx.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/bitops.h>
30 #include <asm/processor.h>
31 #include <asm/mpc512x.h>
32 #include <fdt_support.h>
34 DECLARE_GLOBAL_DATA_PTR;
37 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
38 CLOCK_SCCR1_LPC_EN | \
39 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
40 CLOCK_SCCR1_PSCFIFO_EN | \
41 CLOCK_SCCR1_DDR_EN | \
42 CLOCK_SCCR1_FEC_EN | \
43 CLOCK_SCCR1_NFC_EN | \
44 CLOCK_SCCR1_PCI_EN | \
47 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
50 int eeprom_write_enable(unsigned dev_addr, int state)
52 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
54 if (dev_addr != CONFIG_SYS_I2C_EEPROM_ADDR)
58 setbits_be32(&im->gpio.gpdat, 0x00100000);
60 clrbits_be32(&im->gpio.gpdat, 0x00100000);
65 int board_early_init_f(void)
67 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
72 * Initialize Local Window for NOR FLASH access
74 out_be32(&im->sysconf.lpcs0aw,
75 CSAW_START(CONFIG_SYS_FLASH_BASE) |
76 CSAW_STOP(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE));
77 sync_law(&im->sysconf.lpcs0aw);
80 * Initialize Local Window for boot access
82 out_be32(&im->sysconf.lpbaw,
83 CSAW_START(0xffb00000) | CSAW_STOP(0xffb00000, 0x00010000));
84 sync_law(&im->sysconf.lpbaw);
87 * Initialize Local Window for VPC3 access
89 out_be32(&im->sysconf.lpcs1aw,
90 CSAW_START(CONFIG_SYS_VPC3_BASE) |
91 CSAW_STOP(CONFIG_SYS_VPC3_BASE, CONFIG_SYS_VPC3_SIZE));
92 sync_law(&im->sysconf.lpcs1aw);
95 * Configure Flash Speed
97 out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
100 * Configure VPC3 Speed
102 out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG);
104 spridr = in_be32(&im->sysconf.spridr);
105 if (SVR_MJREV(spridr) >= 2)
106 out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
111 out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
112 out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
113 #if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
114 setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
118 * Configure MSCAN clocks
120 for (i=0; i<4; ++i) {
121 out_be32(&im->clk.msccr[i], 0x00300000);
122 out_be32(&im->clk.msccr[i], 0x00310000);
128 clrbits_be32(&im->gpio.gpodr, 0x000000e0);
129 clrbits_be32(&im->gpio.gpdir, 0x00ef0000);
130 setbits_be32(&im->gpio.gpdir, 0x001000e0);
131 setbits_be32(&im->gpio.gpdat, 0x00100000);
136 phys_size_t initdram(int board_type)
138 return get_ram_size(0, fixed_sdram(NULL, NULL, 0));
141 int misc_init_r(void)
143 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
147 * Optimize access to profibus chip (VPC3) on the local bus
151 * Select 1:1 for LPC_DIV
153 val = in_be32(&im->clk.scfr[0]) & ~SCFR1_LPC_DIV_MASK;
154 out_be32(&im->clk.scfr[0], val | (0x1 << SCFR1_LPC_DIV_SHIFT));
157 * Configure LPC Chips Select Deadcycle Control Register
158 * CS0 - device can drive data 2 clock cycle(s) after CS deassertion
159 * CS1 - device can drive data 1 clock cycle(s) after CS deassertion
161 clrbits_be32(&im->lpc.cs_dccr, 0x000000ff);
162 setbits_be32(&im->lpc.cs_dccr, (0x00 << 4) | (0x01 << 0));
165 * Configure LPC Chips Select Holdcycle Control Register
166 * CS0 - data is valid 2 clock cycle(s) after CS deassertion
167 * CS1 - data is valid 1 clock cycle(s) after CS deassertion
169 clrbits_be32(&im->lpc.cs_hccr, 0x000000ff);
170 setbits_be32(&im->lpc.cs_hccr, (0x00 << 4) | (0x01 << 0));
175 static iopin_t ioregs_init[] = {
176 /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
178 offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
179 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
180 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
182 /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
184 offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
185 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
186 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
188 /* FUNC1=SELECT LPC_CS1 */
190 offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
191 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
192 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
194 /* FUNC3=SELECT PSC5_2 */
196 offsetof(struct ioctrl512x, io_control_psc5_2), 1, 0,
197 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
198 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
200 /* FUNC3=SELECT PSC5_3 */
202 offsetof(struct ioctrl512x, io_control_psc5_3), 1, 0,
203 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
204 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
206 /* FUNC3=SELECT PSC7_3 */
208 offsetof(struct ioctrl512x, io_control_psc7_3), 1, 0,
209 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
210 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
212 /* FUNC3=SELECT PSC9_0 */
214 offsetof(struct ioctrl512x, io_control_psc9_0), 3, 0,
215 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
216 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
218 /* FUNC3=SELECT PSC10_0 */
220 offsetof(struct ioctrl512x, io_control_psc10_0), 3, 0,
221 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
222 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
224 /* FUNC3=SELECT PSC10_3 */
226 offsetof(struct ioctrl512x, io_control_psc10_3), 1, 0,
227 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
228 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
230 /* FUNC3=SELECT PSC11_0 */
232 offsetof(struct ioctrl512x, io_control_psc11_0), 4, 0,
233 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
234 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
236 /* FUNC0=SELECT IRQ0 */
238 offsetof(struct ioctrl512x, io_control_irq0), 4, 0,
239 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
240 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
244 static iopin_t rev2_silicon_pci_ioregs_init[] = {
245 /* FUNC0=PCI Sets next 54 to PCI pads */
247 offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
248 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
254 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
257 puts("Board: MECP_5123\n");
260 * Initialize function mux & slew rate IO inter alia on IO
263 iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
265 spridr = in_be32(&im->sysconf.spridr);
266 if (SVR_MJREV(spridr) >= 2)
267 iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
272 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
273 void ft_board_setup(void *blob, bd_t *bd)
275 ft_cpu_setup(blob, bd);
277 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */