2 * (C) Copyright 2001-2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/processor.h>
35 #ifdef CONFIG_VIDEO_SM501
37 #define SWAP32(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
38 (((x) & 0x00ff0000) >> 8) | (((x) & 0xff000000) >> 24) )
40 #ifdef CONFIG_VIDEO_SM501_8BPP
41 #error CONFIG_VIDEO_SM501_8BPP not supported.
42 #endif /* CONFIG_VIDEO_SM501_8BPP */
44 #ifdef CONFIG_VIDEO_SM501_16BPP
48 * 800x600 display B084SN03: PCLK = 40MHz
53 static const SMI_REGS init_regs_800x600 [] =
56 {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
58 {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
60 {0x00004, SWAP32(0x00000000)},
61 /* clocks for pm1... */
62 {0x00048, SWAP32(0x00021807)},
63 {0x0004C, SWAP32(0x221a0a01)},
64 {0x00054, SWAP32(0x00000001)},
65 /* clocks for pm0... */
66 {0x00040, SWAP32(0x00021807)},
67 {0x00044, SWAP32(0x221a0a01)},
68 {0x00054, SWAP32(0x00000000)},
69 /* panel control regs... */
70 {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
71 {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
72 {0x8000C, SWAP32(0x00000000)}, /* panel fb address */
73 {0x80010, SWAP32(0x06400640)}, /* panel fb offset/window width */
74 {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
75 {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
76 {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
77 {0x80020, SWAP32(0x02580320)}, /* panel plane br location */
78 {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
79 {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
80 {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
81 {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
82 {0x80200, SWAP32(0x00010000)}, /* crt display control */
87 * 1024x768 display G150XG02: PCLK = 65MHz
92 static const SMI_REGS init_regs_1024x768 [] =
94 {0x00004, SWAP32(0x00000000)},
95 /* clocks for pm1... */
96 {0x00048, SWAP32(0x00021807)},
97 {0x0004C, SWAP32(0x011a0a01)},
98 {0x00054, SWAP32(0x00000001)},
99 /* clocks for pm0... */
100 {0x00040, SWAP32(0x00021807)},
101 {0x00044, SWAP32(0x011a0a01)},
102 {0x00054, SWAP32(0x00000000)},
103 /* panel control regs... */
104 {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
105 {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
106 {0x8000C, SWAP32(0x00000000)}, /* panel fb address */
107 {0x80010, SWAP32(0x08000800)}, /* panel fb offset/window width */
108 {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
109 {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
110 {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
111 {0x80020, SWAP32(0x03000400)}, /* panel plane br location */
112 {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
113 {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
114 {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
115 {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
116 {0x80200, SWAP32(0x00010000)}, /* crt display control */
120 #endif /* CONFIG_VIDEO_SM501_16BPP */
122 #ifdef CONFIG_VIDEO_SM501_32BPP
126 * 800x600 display B084SN03: PCLK = 40MHz
131 static const SMI_REGS init_regs_800x600 [] =
133 #if 0 /* test-only */
134 {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
136 {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
138 {0x00004, SWAP32(0x00000000)},
139 /* clocks for pm1... */
140 {0x00048, SWAP32(0x00021807)},
141 {0x0004C, SWAP32(0x221a0a01)},
142 {0x00054, SWAP32(0x00000001)},
143 /* clocks for pm0... */
144 {0x00040, SWAP32(0x00021807)},
145 {0x00044, SWAP32(0x221a0a01)},
146 {0x00054, SWAP32(0x00000000)},
147 /* panel control regs... */
148 {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
149 {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
150 {0x8000C, SWAP32(0x00000000)}, /* panel fb address */
151 {0x80010, SWAP32(0x0c800c80)}, /* panel fb offset/window width */
152 {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
153 {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
154 {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
155 {0x80020, SWAP32(0x02580320)}, /* panel plane br location */
156 {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
157 {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
158 {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
159 {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
160 {0x80200, SWAP32(0x00010000)}, /* crt display control */
165 * 1024x768 display G150XG02: PCLK = 65MHz
170 static const SMI_REGS init_regs_1024x768 [] =
172 {0x00004, SWAP32(0x00000000)},
173 /* clocks for pm1... */
174 {0x00048, SWAP32(0x00021807)},
175 {0x0004C, SWAP32(0x011a0a01)},
176 {0x00054, SWAP32(0x00000001)},
177 /* clocks for pm0... */
178 {0x00040, SWAP32(0x00021807)},
179 {0x00044, SWAP32(0x011a0a01)},
180 {0x00054, SWAP32(0x00000000)},
181 /* panel control regs... */
182 {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
183 {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
184 {0x8000C, SWAP32(0x00000000)}, /* panel fb address */
185 {0x80010, SWAP32(0x10001000)}, /* panel fb offset/window width */
186 {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
187 {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
188 {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
189 {0x80020, SWAP32(0x03000400)}, /* panel plane br location */
190 {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
191 {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
192 {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
193 {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
194 {0x80200, SWAP32(0x00010000)}, /* crt display control */
198 #endif /* CONFIG_VIDEO_SM501_32BPP */
200 #endif /* CONFIG_VIDEO_SM501 */
206 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
207 extern void lxt971_no_sleep(void);
209 /* fpga configuration data - gzip compressed and generated by bin2c */
210 const unsigned char fpgadata[] =
212 #include "fpgadata.c"
216 * include common fpga code (for esd boards)
218 #include "../common/fpga.c"
222 int gunzip(void *, int, unsigned char *, unsigned long *);
225 /* logo bitmap data - gzip compressed and generated by bin2c */
226 unsigned char logo_bmp_320[] =
228 #include "logo_320_240_4bpp.c"
231 unsigned char logo_bmp_320_8bpp[] =
233 #include "logo_320_240_8bpp.c"
236 unsigned char logo_bmp_640[] =
238 #include "logo_640_480_24bpp.c"
241 unsigned char logo_bmp_1024[] =
243 #include "logo_1024_768_8bpp.c"
248 * include common lcd code (for esd boards)
250 #include "../common/lcd.c"
252 #include "../common/s1d13704_320_240_4bpp.h"
253 #include "../common/s1d13705_320_240_8bpp.h"
254 #include "../common/s1d13806_640_480_16bpp.h"
255 #include "../common/s1d13806_1024_768_8bpp.h"
259 * include common auto-update code (for esd boards)
261 #include "../common/auto_update.h"
263 au_image_t au_image[] = {
264 {"hh405/preinst.img", 0, -1, AU_SCRIPT},
265 {"hh405/u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE},
266 {"hh405/pImage_${bd_type}", 0x00000000, 0x00100000, AU_NAND},
267 {"hh405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND},
268 {"hh405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND},
269 {"hh405/postinst.img", 0, 0, AU_SCRIPT},
272 int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
275 int board_revision(void)
277 unsigned long osrh_reg;
278 unsigned long isr1h_reg;
279 unsigned long tcr_reg;
283 * Get version of HH405 board from GPIO's
287 * Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO)
289 osrh_reg = in32(GPIO0_OSRH);
290 isr1h_reg = in32(GPIO0_ISR1H);
291 tcr_reg = in32(GPIO0_TCR);
292 out32(GPIO0_OSRH, osrh_reg & ~0xC0003000); /* output select */
293 out32(GPIO0_ISR1H, isr1h_reg | 0xC0003000); /* input select */
294 out32(GPIO0_TCR, tcr_reg & ~0x80400000); /* select input */
296 udelay(1000); /* wait some time before reading input */
297 value = in32(GPIO0_IR) & 0x80400000; /* get config bits */
300 * Restore GPIO settings
302 out32(GPIO0_OSRH, osrh_reg); /* output select */
303 out32(GPIO0_ISR1H, isr1h_reg); /* input select */
304 out32(GPIO0_TCR, tcr_reg); /* enable output driver for outputs */
306 if (value & 0x80000000) {
307 /* Revision 1.0 or 1.1 detected */
310 if (value & 0x00400000) {
314 /* Revision >= 2.0 detected */
315 /* rev. 2.x uses four SM501 GPIOs for revision coding */
322 int board_early_init_f (void)
325 * IRQ 0-15 405GP internally generated; active high; level sensitive
326 * IRQ 16 405GP internally generated; active low; level sensitive
328 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
329 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
330 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
331 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
332 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
333 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
334 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
336 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
337 mtdcr(uicer, 0x00000000); /* disable all ints */
338 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
339 mtdcr(uicpr, CFG_UIC0_POLARITY);/* set int polarities */
340 mtdcr(uictr, 0x10000000); /* set int trigger levels */
341 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
342 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
345 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
347 mtebc (epcr, 0xa8400000); /* ebc always driven */
353 int misc_init_r (void)
355 DECLARE_GLOBAL_DATA_PTR;
357 volatile unsigned short *fpga_ctrl =
358 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
359 volatile unsigned short *lcd_contrast =
360 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4);
361 volatile unsigned short *lcd_backlight =
362 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6);
364 ulong len = sizeof(fpgadata);
369 unsigned long contrast0 = 0xffffffff;
371 dst = malloc(CFG_FPGA_MAX_SIZE);
372 if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
373 printf ("GUNZIP ERROR - must RESET board to recover\n");
374 do_reset (NULL, 0, 0, NULL);
377 status = fpga_boot(dst, len);
379 printf("\nFPGA: Booting failed ");
381 case ERROR_FPGA_PRG_INIT_LOW:
382 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
384 case ERROR_FPGA_PRG_INIT_HIGH:
385 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
387 case ERROR_FPGA_PRG_DONE:
388 printf("(Timeout: DONE not high after programming FPGA)\n ");
392 /* display infos on fpgaimage */
394 for (i=0; i<4; i++) {
396 printf("FPGA: %s\n", &(dst[index+1]));
401 for (i=20; i>0; i--) {
402 printf("Rebooting in %2d seconds \r",i);
403 for (index=0;index<1000;index++)
407 do_reset(NULL, 0, 0, NULL);
412 /* display infos on fpgaimage */
414 for (i=0; i<4; i++) {
416 printf("%s ", &(dst[index+1]));
424 * Reset FPGA via FPGA_INIT pin
426 out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
427 out32(GPIO0_OR, in32(GPIO0_OR) & ~FPGA_INIT); /* reset low */
428 udelay(1000); /* wait 1ms */
429 out32(GPIO0_OR, in32(GPIO0_OR) | FPGA_INIT); /* reset high */
430 udelay(1000); /* wait 1ms */
433 * Write Board revision into FPGA
435 *fpga_ctrl |= gd->board_type & 0x0003;
436 if (gd->board_type >= 0x0200) {
437 *fpga_ctrl |= CFG_FPGA_CTRL_CF_BUS_EN;
441 * Setup and enable EEPROM write protection
443 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
446 * Set NAND-FLASH GPIO signals to default
448 out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
449 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
452 * Reset touch-screen controller
454 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_TOUCH_RST);
456 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_TOUCH_RST);
459 * Enable power on PS/2 interface (with reset)
461 *fpga_ctrl &= ~(CFG_FPGA_CTRL_PS2_PWR);
464 *fpga_ctrl |= (CFG_FPGA_CTRL_PS2_PWR);
467 * Get contrast value from environment variable
469 str = getenv("contrast0");
471 contrast0 = simple_strtol(str, NULL, 16);
472 if (contrast0 > 255) {
473 printf("ERROR: contrast0 value too high (0x%lx)!\n", contrast0);
479 * Init lcd interface and display logo
482 str = getenv("bd_type");
483 if (strcmp(str, "ppc230") == 0) {
485 * Switch backlight on
487 *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL;
488 *lcd_backlight = 0x0000;
491 lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
492 regs_13806_1024_768_8bpp,
493 sizeof(regs_13806_1024_768_8bpp)/sizeof(regs_13806_1024_768_8bpp[0]),
494 logo_bmp_1024, sizeof(logo_bmp_1024));
495 } else if (strcmp(str, "ppc220") == 0) {
497 * Switch backlight on
499 *fpga_ctrl &= ~CFG_FPGA_CTRL_VGA0_BL;
500 *lcd_backlight = 0x0000;
503 lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
504 regs_13806_640_480_16bpp,
505 sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
506 logo_bmp_640, sizeof(logo_bmp_640));
507 } else if (strcmp(str, "ppc215") == 0) {
509 * Set default display contrast voltage
511 if (contrast0 == 0xffffffff) {
512 *lcd_contrast = 0x0082;
514 *lcd_contrast = contrast0;
516 *lcd_backlight = 0xffff;
518 * Switch backlight on
520 *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE;
522 * Set lcd clock (small epson)
524 *fpga_ctrl |= LCD_CLK_06250;
525 udelay(100); /* wait for 100 us */
528 lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
529 regs_13705_320_240_8bpp,
530 sizeof(regs_13705_320_240_8bpp)/sizeof(regs_13705_320_240_8bpp[0]),
531 logo_bmp_320_8bpp, sizeof(logo_bmp_320_8bpp));
532 } else if (strcmp(str, "ppc210") == 0) {
534 * Set default display contrast voltage
536 if (contrast0 == 0xffffffff) {
537 *lcd_contrast = 0x0060;
539 *lcd_contrast = contrast0;
541 *lcd_backlight = 0xffff;
543 * Switch backlight on
545 *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE;
547 * Set lcd clock (small epson)
549 *fpga_ctrl |= LCD_CLK_08330;
552 lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
553 regs_13704_320_240_4bpp,
554 sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
555 logo_bmp_320, sizeof(logo_bmp_320));
556 #ifdef CONFIG_VIDEO_SM501
561 * Is SM501 connected (ppc221/ppc231)?
563 devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
564 if (devbusfn != -1) {
565 puts("VGA: SM501 with 8 MB ");
566 if (strcmp(str, "ppc221") == 0) {
567 printf("(800*600, %dbpp)\n", BPP);
568 } else if (strcmp(str, "ppc231") == 0) {
569 printf("(1024*768, %dbpp)\n", BPP);
571 printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
575 printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
578 #endif /* CONFIG_VIDEO_SM501 */
586 * Check Board Identity:
589 int checkboard (void)
591 DECLARE_GLOBAL_DATA_PTR;
594 int i = getenv_r ("serial#", str, sizeof(str));
599 puts ("### No HW ID - assuming HH405");
604 if (getenv_r("bd_type", str, sizeof(str)) != -1) {
607 puts(" (Missing bd_type!");
610 gd->board_type = board_revision();
611 printf(", Rev %ld.%ld)\n",
612 (gd->board_type >> 8) & 0xff,
613 gd->board_type & 0xff);
616 * Disable sleep mode in LXT971
624 long int initdram (int board_type)
628 mtdcr(memcfga, mem_mb0cf);
629 val = mfdcr(memcfgd);
632 printf("\nmb0cf=%x\n", val); /* test-only */
633 printf("strap=%x\n", mfdcr(strap)); /* test-only */
636 return (4*1024*1024 << ((val & 0x000e0000) >> 17));
642 /* TODO: XXX XXX XXX */
643 printf ("test: 16 MB - ok\n");
649 #ifdef CONFIG_IDE_RESET
650 void ide_set_reset(int on)
652 volatile unsigned short *fpga_mode =
653 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
656 * Assert or deassert CompactFlash Reset Pin
658 if (on) { /* assert RESET */
659 *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
660 } else { /* release RESET */
661 *fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
664 #endif /* CONFIG_IDE_RESET */
667 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
668 #include <linux/mtd/nand_legacy.h>
669 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
673 nand_probe(CFG_NAND_BASE);
674 if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
675 print_size(nand_dev_desc[0].totlen, "\n");
681 #if defined(CFG_EEPROM_WREN)
682 /* Input: <dev_addr> I2C address of EEPROM device to enable.
683 * <state> -1: deliver current state
686 * Returns: -1: wrong device address
687 * 0: dis-/en- able done
688 * 0/1: current state if <state> was -1.
690 int eeprom_write_enable (unsigned dev_addr, int state)
692 if (CFG_I2C_EEPROM_ADDR != dev_addr) {
697 /* Enable write access, clear bit GPIO_SINT2. */
698 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
702 /* Disable write access, set bit GPIO_SINT2. */
703 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
707 /* Read current status back. */
708 state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
715 int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
717 int query = argc == 1;
721 /* Query write access state. */
722 state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
724 puts ("Query of write access state failed.\n");
726 printf ("Write access for device 0x%0x is %sabled.\n",
727 CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
731 if ('0' == argv[1][0]) {
732 /* Disable write access. */
733 state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
735 /* Enable write access. */
736 state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
739 puts ("Setup of write access state failed.\n");
746 U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
747 "eepwren - Enable / disable / query EEPROM write access\n",
749 #endif /* #if defined(CFG_EEPROM_WREN) */
752 #ifdef CONFIG_VIDEO_SM501
753 #ifdef CONFIG_CONSOLE_EXTRA_INFO
755 * Return text to be printed besides the logo.
757 void video_get_info_str (int line_number, char *info)
759 DECLARE_GLOBAL_DATA_PTR;
763 int i = getenv_r("serial#", str2, sizeof(str));
765 if (line_number == 1) {
766 sprintf(str, " Board: ");
769 strcat(str, "### No HW ID - assuming HH405");
774 if (getenv_r("bd_type", str2, sizeof(str2)) != -1) {
778 strcat(str, " (Missing bd_type!");
781 sprintf(str2, ", Rev %ld.%ld)",
782 (gd->board_type >> 8) & 0xff, gd->board_type & 0xff);
789 #endif /* CONFIG_CONSOLE_EXTRA_INFO */
792 * Returns SM501 register base address. First thing called in the driver.
794 unsigned int board_video_init (void)
800 * Is SM501 connected (ppc221/ppc231)?
802 devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
803 if (devbusfn != -1) {
804 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, (u32 *)&addr);
805 return (addr & 0xfffffffe);
812 * Returns SM501 framebuffer address
814 unsigned int board_video_get_fb (void)
820 * Is SM501 connected (ppc221/ppc231)?
822 devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
823 if (devbusfn != -1) {
824 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (u32 *)&addr);
825 return (addr & 0xfffffffe);
832 * Called after initializing the SM501 and before clearing the screen.
834 void board_validate_screen (unsigned int base)
839 * Return a pointer to the initialization sequence.
841 const SMI_REGS *board_get_regs (void)
845 str = getenv("bd_type");
846 if (strcmp(str, "ppc221") == 0) {
847 return init_regs_800x600;
849 return init_regs_1024x768;
853 int board_get_width (void)
857 str = getenv("bd_type");
858 if (strcmp(str, "ppc221") == 0) {
865 int board_get_height (void)
869 str = getenv("bd_type");
870 if (strcmp(str, "ppc221") == 0) {
877 #endif /* CONFIG_VIDEO_SM501 */