3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * cpci5200.c - main board support/init for the esd cpci5200.
36 #include "mt46v16m16-75.h"
38 void init_ata_reset(void);
40 static void sdram_start(int hi_addr)
42 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
44 /* unlock mode register */
45 *(vu_long *) MPC5XXX_SDRAM_CTRL =
46 SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
47 __asm__ volatile ("sync");
49 /* precharge all banks */
50 *(vu_long *) MPC5XXX_SDRAM_CTRL =
51 SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
52 __asm__ volatile ("sync");
54 /* set mode register: extended mode */
55 *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
56 __asm__ volatile ("sync");
58 /* set mode register: reset DLL */
59 *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
60 __asm__ volatile ("sync");
62 /* precharge all banks */
63 *(vu_long *) MPC5XXX_SDRAM_CTRL =
64 SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
65 __asm__ volatile ("sync");
68 *(vu_long *) MPC5XXX_SDRAM_CTRL =
69 SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
70 __asm__ volatile ("sync");
72 /* set mode register */
73 *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
74 __asm__ volatile ("sync");
76 /* normal operation */
77 *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
78 __asm__ volatile ("sync");
82 * ATTENTION: Although partially referenced initdram does NOT make real use
83 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
84 * is something else than 0x00000000.
87 phys_size_t initdram(int board_type)
92 /* setup SDRAM chip selects */
93 *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
94 *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
95 __asm__ volatile ("sync");
97 /* setup config registers */
98 *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
99 *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
100 __asm__ volatile ("sync");
103 *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
104 __asm__ volatile ("sync");
106 /* find RAM size using SDRAM CS0 only */
108 test1 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000);
110 test2 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000);
119 /* memory smaller than 1MB is impossible */
120 if (dramsize < (1 << 20)) {
124 /* set SDRAM CS0 size according to the amount of RAM found */
126 *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
127 0x13 + __builtin_ffs(dramsize >> 20) - 1;
128 /* let SDRAM CS1 start right after CS0 */
129 *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
132 *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
133 /* let SDRAM CS1 start right after CS0 */
134 *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
136 *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
137 0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
138 /* let SDRAM CS1 start right after CS0 */
139 *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e; /* 2G */
144 /* find RAM size using SDRAM CS1 only */
146 get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
148 get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
151 /* set SDRAM CS1 size according to the amount of RAM found */
153 *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
161 puts("Board: esd CPCI5200 (cpci5200)\n");
165 void flash_preinit(void)
168 * Now, when we are in RAM, enable flash write
169 * access for detection process.
170 * Note that CS_BOOT cannot be cleared when
171 * executing in flash.
173 *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
176 void flash_afterinit(ulong size)
178 if (size == 0x02000000) {
180 *(vu_long *) MPC5XXX_BOOTCS_START =
181 *(vu_long *) MPC5XXX_CS0_START =
182 START_REG(CFG_BOOTCS_START | size);
183 *(vu_long *) MPC5XXX_BOOTCS_STOP =
184 *(vu_long *) MPC5XXX_CS0_STOP =
185 STOP_REG(CFG_BOOTCS_START | size, size);
190 static struct pci_controller hose;
192 extern void pci_mpc5xxx_init(struct pci_controller *);
194 void pci_init_board(void) {
195 pci_mpc5xxx_init(&hose);
199 #if defined(CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET)
201 void init_ide_reset(void)
203 debug("init_ide_reset\n");
205 /* Configure PSC1_4 as GPIO output for ATA reset */
206 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
207 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
210 void ide_set_reset(int idereset)
212 debug("ide_reset(%d)\n", idereset);
215 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
217 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
222 #define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004)
223 #define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C)
224 #define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x0010)
225 #define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT (MPC5XXX_GPIO + 0x0014)
227 #define MPC5XXX_INTERRUPT_GPIO_ENABLE (MPC5XXX_GPIO + 0x0020)
228 #define MPC5XXX_INTERRUPT_GPIO_DIR (MPC5XXX_GPIO + 0x0028)
229 #define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
230 #define MPC5XXX_INTERRUPT_GPIO_STATUS (MPC5XXX_GPIO + 0x003C)
232 #define GPIO_WU6 0x40000000UL
233 #define GPIO_USB0 0x00010000UL
234 #define GPIO_USB9 0x08000000UL
235 #define GPIO_USB9S 0x00080000UL
237 void init_ata_reset(void)
239 debug("init_ata_reset\n");
241 /* Configure GPIO_WU6 as GPIO output for ATA reset */
242 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
243 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
244 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
245 __asm__ volatile ("sync");
247 *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
248 *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
249 *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
250 __asm__ volatile ("sync");
252 *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
253 *(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
254 __asm__ volatile ("sync");
256 if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
257 *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
258 __asm__ volatile ("sync");
262 int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
267 volatile unsigned long *ptr;
269 addr = simple_strtol(argv[1], NULL, 16);
270 size = simple_strtol(argv[2], NULL, 16);
272 printf("\nWriting at addr %08x, size %08x.\n", addr, size);
275 ptr = (volatile unsigned long *)addr;
276 for (i = 0; i < (size >> 2); i++) {
280 /* Abort if ctrl-c was pressed */
290 U_BOOT_CMD(writepci, 3, 1, do_writepci,
291 "writepci- Write some data to pcibus\n",
292 "<addr> <size>\n" " - Write some data to pcibus.\n");