2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <fdt_support.h>
10 #include <asm/processor.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 extern void __ft_board_setup(void *blob, bd_t *bd);
23 /* fpga configuration data - generated by bin2cc */
24 const unsigned char fpgadata[] =
26 #if defined(CONFIG_CPCI405_VER2)
27 # if defined(CONFIG_CPCI405AB)
28 # include "fpgadata_cpci405ab.c"
30 # include "fpgadata_cpci4052.c"
33 # include "fpgadata_cpci405.c"
38 * include common fpga code (for esd boards)
40 #include "../common/fpga.c"
41 #include "../common/auto_update.h"
43 #if defined(CONFIG_CPCI405AB)
44 au_image_t au_image[] = {
45 {"cpci405ab/preinst.img", 0, -1, AU_SCRIPT},
46 {"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR},
47 {"cpci405ab/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
48 {"cpci405ab/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
49 {"cpci405ab/postinst.img", 0, 0, AU_SCRIPT},
52 #if defined(CONFIG_CPCI405_VER2)
53 au_image_t au_image[] = {
54 {"cpci4052/preinst.img", 0, -1, AU_SCRIPT},
55 {"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR},
56 {"cpci4052/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
57 {"cpci4052/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
58 {"cpci4052/postinst.img", 0, 0, AU_SCRIPT},
61 au_image_t au_image[] = {
62 {"cpci405/preinst.img", 0, -1, AU_SCRIPT},
63 {"cpci405/pImage", 0xffc00000, 0x000c0000, AU_NOR},
64 {"cpci405/pImage.initrd", 0xffcc0000, 0x00310000, AU_NOR},
65 {"cpci405/u-boot.img", 0xfffd0000, 0x00030000, AU_FIRMWARE},
66 {"cpci405/postinst.img", 0, 0, AU_SCRIPT},
71 int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
74 int cpci405_version(void);
75 void lxt971_no_sleep(void);
77 int board_early_init_f(void)
79 #ifndef CONFIG_CPCI405_VER2
85 /* set up serial port with default baudrate */
87 gd->baudrate = CONFIG_BAUDRATE;
93 * First pull fpga-prg pin low,
94 * to disable fpga logic (on version 2 board)
96 out_be32((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */
97 out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
98 out_be32((void *)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
99 out_be32((void *)GPIO0_OR, 0); /* pull prg low */
104 #ifndef CONFIG_CPCI405_VER2
105 if (cpci405_version() == 1) {
106 status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
108 /* booting FPGA failed */
110 /* set up serial port with default baudrate */
112 gd->baudrate = CONFIG_BAUDRATE;
116 printf("\nFPGA: Booting failed ");
118 case ERROR_FPGA_PRG_INIT_LOW:
119 printf("(Timeout: INIT not low after "
120 "asserting PROGRAM*)\n ");
122 case ERROR_FPGA_PRG_INIT_HIGH:
123 printf("(Timeout: INIT not high after "
124 "deasserting PROGRAM*)\n ");
126 case ERROR_FPGA_PRG_DONE:
127 printf("(Timeout: DONE not high after "
128 "programming FPGA)\n ");
132 /* display infos on fpgaimage */
134 for (i = 0; i < 4; i++) {
135 len = fpgadata[index];
136 printf("FPGA: %s\n", &(fpgadata[index + 1]));
141 for (i = 20; i > 0; i--) {
142 printf("Rebooting in %2d seconds \r",i);
143 for (index = 0; index < 1000; index++)
147 do_reset(NULL, 0, 0, NULL);
150 #endif /* !CONFIG_CPCI405_VER2 */
153 * IRQ 0-15 405GP internally generated; active high; level sensitive
154 * IRQ 16 405GP internally generated; active low; level sensitive
156 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
157 * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052); active low; level sens.
158 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
159 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
160 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
161 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
162 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
164 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
165 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
166 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
167 #if defined(CONFIG_CPCI405_6U)
168 if (cpci405_version() == 3) {
169 mtdcr(UIC0PR, 0xFFFFFF99); /* set int polarities */
171 mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
174 mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
176 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
177 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,
178 * INT0 highest priority */
179 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
186 #if defined(CONFIG_CPCI405_VER2)
187 return 0; /* no, board is cpci405 */
189 if ((in_8((void*)0xf0000400) == 0x00) &&
190 (in_8((void*)0xf0000401) == 0x01))
191 return 0; /* no, board is cpci405 */
193 return -1; /* yes, board is cterm-m2 */
197 int cpci405_host(void)
199 if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN)
200 return -1; /* yes, board is cpci405 host */
202 return 0; /* no, board is cpci405 adapter */
205 int cpci405_version(void)
207 unsigned long CPC0_CR0Reg;
211 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
213 CPC0_CR0Reg = mfdcr(CPC0_CR0);
214 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000);
215 out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
216 out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
217 udelay(1000); /* wait some time before reading input */
218 value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
221 * Restore GPIO settings
223 mtdcr(CPC0_CR0, CPC0_CR0Reg);
227 /* CS2==1 && CS3==1 -> version 1 */
230 /* CS2==0 && CS3==1 -> version 2 */
233 /* CS2==1 && CS3==0 -> version 3 or 6U board */
236 /* CS2==0 && CS3==0 -> version 4 */
239 /* should not be reached! */
244 int misc_init_r (void)
246 unsigned long CPC0_CR0Reg;
248 /* adjust flash start and offset */
249 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
250 gd->bd->bi_flashoffset = 0;
252 #if defined(CONFIG_CPCI405_VER2)
255 ulong len = sizeof(fpgadata);
261 * On CPCI-405 version 2 the environment is saved in eeprom!
262 * FPGA can be gzip compressed (malloc) and booted this late.
264 if (cpci405_version() >= 2) {
266 * Setup GPIO pins (CS6+CS7 as GPIO)
268 CPC0_CR0Reg = mfdcr(CPC0_CR0);
269 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
271 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
272 if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
273 (uchar *)fpgadata, &len) != 0) {
274 printf("GUNZIP ERROR - must RESET board to recover\n");
275 do_reset(NULL, 0, 0, NULL);
278 status = fpga_boot(dst, len);
280 printf("\nFPGA: Booting failed ");
282 case ERROR_FPGA_PRG_INIT_LOW:
283 printf("(Timeout: INIT not low after "
284 "asserting PROGRAM*)\n ");
286 case ERROR_FPGA_PRG_INIT_HIGH:
287 printf("(Timeout: INIT not high after "
288 "deasserting PROGRAM*)\n ");
290 case ERROR_FPGA_PRG_DONE:
291 printf("(Timeout: DONE not high after "
292 "programming FPGA)\n ");
296 /* display infos on fpgaimage */
298 for (i = 0; i < 4; i++) {
300 printf("FPGA: %s\n", &(dst[index + 1]));
305 for (i = 20; i > 0; i--) {
306 printf("Rebooting in %2d seconds \r", i);
307 for (index = 0; index < 1000; index++)
311 do_reset(NULL, 0, 0, NULL);
314 /* restore gpio/cs settings */
315 mtdcr(CPC0_CR0, CPC0_CR0Reg);
319 /* display infos on fpgaimage */
321 for (i = 0; i < 4; i++) {
323 printf("%s ", &(dst[index + 1]));
331 * Reset FPGA via FPGA_DATA pin
333 SET_FPGA(FPGA_PRG | FPGA_CLK);
334 udelay(1000); /* wait 1ms */
335 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
336 udelay(1000); /* wait 1ms */
338 #if defined(CONFIG_CPCI405_6U)
339 #error HIER GETH ES WEITER MIT IO ACCESSORS
340 if (cpci405_version() == 3) {
342 * Enable outputs in fpga on version 3 board
344 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
345 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
346 CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT);
351 out_8((void*)CONFIG_SYS_LED_ADDR, 0x00);
354 * Reset external DUART
356 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
357 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
358 CONFIG_SYS_FPGA_MODE_DUART_RESET);
360 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
361 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
362 ~CONFIG_SYS_FPGA_MODE_DUART_RESET);
367 puts("\n*** U-Boot Version does not match Board Version!\n");
368 puts("*** CPCI-405 Version 1.x detected!\n");
369 puts("*** Please use correct U-Boot version "
370 "(CPCI405 instead of CPCI4052)!\n\n");
373 #else /* CONFIG_CPCI405_VER2 */
374 if (cpci405_version() >= 2) {
375 puts("\n*** U-Boot Version does not match Board Version!\n");
376 puts("*** CPCI-405 Board Version 2.x detected!\n");
377 puts("*** Please use correct U-Boot version "
378 "(CPCI4052 instead of CPCI405)!\n\n");
380 #endif /* CONFIG_CPCI405_VER2 */
383 * Select cts (and not dsr) on uart1
385 CPC0_CR0Reg = mfdcr(CPC0_CR0);
386 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
392 * Check Board Identity:
397 #ifndef CONFIG_CPCI405_VER2
402 int i = getenv_f("serial#", str, sizeof(str));
408 puts("### No HW ID - assuming CPCI405");
412 ver = cpci405_version();
413 printf(" (Ver %d.x, ", ver);
419 * Read board-id and save in env-variable
421 sprintf(str, "%d", *(unsigned char *)0xf0000400);
422 setenv("boardid", str);
423 printf("CTERM-M2 - Id=%s)", str);
426 puts("PCI Host Version)");
428 puts("PCI Adapter Version)");
431 #ifndef CONFIG_CPCI405_VER2
434 /* display infos on fpgaimage */
436 for (i = 0; i < 4; i++) {
437 len = fpgadata[index];
438 printf("%s ", &(fpgadata[index + 1]));
449 #if defined(CONFIG_LXT971_NO_SLEEP)
452 * Disable sleep mode in LXT971
458 #if defined(CONFIG_CPCI405_VER2) && defined (CONFIG_IDE_RESET)
459 void ide_set_reset(int on)
462 * Assert or deassert CompactFlash Reset Pin
464 if (on) { /* assert RESET */
465 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
466 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
467 ~CONFIG_SYS_FPGA_MODE_CF_RESET);
468 } else { /* release RESET */
469 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
470 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
471 CONFIG_SYS_FPGA_MODE_CF_RESET);
475 #endif /* CONFIG_IDE_RESET && CONFIG_CPCI405_VER2 */
477 #if defined(CONFIG_PCI)
478 void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
480 unsigned char int_line = 0xff;
483 * Write pci interrupt line register (cpci405 specific)
485 switch (PCI_DEV(dev) & 0x03) {
500 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
503 int pci_pre_init(struct pci_controller *hose)
505 hose->fixup_irq = cpci405_pci_fixup_irq;
508 #endif /* defined(CONFIG_PCI) */
510 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
511 void ft_board_setup(void *blob, bd_t *bd)
515 __ft_board_setup(blob, bd);
518 * Disable PCI in adapter mode.
520 if (!cpci405_host()) {
521 rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status",
522 "disabled", sizeof("disabled"), 1);
524 printf("Unable to update property status in PCI node, "
530 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
532 #if defined(CONFIG_CPCI405AB)
533 #define ONE_WIRE_CLEAR out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
534 CONFIG_SYS_FPGA_MODE), \
535 in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
536 CONFIG_SYS_FPGA_MODE)) | \
537 CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
539 #define ONE_WIRE_SET out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
540 CONFIG_SYS_FPGA_MODE), \
541 in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
542 CONFIG_SYS_FPGA_MODE)) & \
543 ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
545 #define ONE_WIRE_GET (in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
546 CONFIG_SYS_FPGA_STATUS)) & \
547 CONFIG_SYS_FPGA_MODE_1WIRE)
550 * Generate a 1-wire reset, return 1 if no presence detect was found,
551 * return 0 otherwise.
552 * (NOTE: Does not handle alarm presence from DS2404/DS1994)
554 int OWTouchReset(void)
563 result = ONE_WIRE_GET;
570 * Send 1 a 1-wire write bit.
571 * Provide 10us recovery time.
573 void OWWriteBit(int bit)
595 * Read a bit from the 1-wire bus and return it.
596 * Provide 10us recovery time.
607 result = ONE_WIRE_GET;
613 void OWWriteByte(int data)
617 for (loop = 0; loop < 8; loop++) {
618 OWWriteBit(data & 0x01);
625 int loop, result = 0;
627 for (loop = 0; loop < 8; loop++) {
636 int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
641 unsigned char ow_id[6];
645 * Clear 1-wire bit (open drain with pull-up)
647 val = in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
648 CONFIG_SYS_FPGA_MODE));
649 val &= ~CONFIG_SYS_FPGA_MODE_1WIRE; /* clear 1-wire bit */
650 out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
651 CONFIG_SYS_FPGA_MODE), val);
653 result = OWTouchReset();
655 puts("No 1-wire device detected!\n");
657 OWWriteByte(0x33); /* send read rom command */
658 OWReadByte(); /* skip family code ( == 0x01) */
659 for (i = 0; i < 6; i++)
660 ow_id[i] = OWReadByte();
661 OWReadByte(); /* read crc */
663 sprintf(str, "%02X%02X%02X%02X%02X%02X",
664 ow_id[0], ow_id[1], ow_id[2], ow_id[3], ow_id[4], ow_id[5]);
665 printf("Setting environment variable 'ow_id' to %s\n", str);
666 setenv("ow_id", str);
671 onewire, 1, 1, do_onewire,
676 #define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT24WC32 */
677 #define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars */
680 * Write backplane ip-address...
682 int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
690 buf = malloc(CONFIG_ENV_SIZE_2);
691 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0,
692 (uchar *)buf, CONFIG_ENV_SIZE_2))
693 puts("\nError reading backplane EEPROM!\n");
695 crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
696 if (crc != *(ulong *)buf) {
697 printf("ERROR: crc mismatch %08lx %08lx\n",
705 ptr = strstr(buf+4, "bp_ip=");
707 printf("ERROR: bp_ip not found!\n");
711 ipaddr = string_to_ip(ptr);
714 * Update whole ip-addr
716 sprintf(str, "%pI4", &ipaddr);
717 setenv("ipaddr", str);
718 printf("Updated ip_addr from bp_eeprom to %s!\n", str);
726 getbpip, 1, 1, do_get_bpip,
727 "Update IP-Address with Backplane IP-Address",
732 * Set and print backplane ip...
734 int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
745 printf("Setting bp_ip to %s\n", argv[1]);
746 buf = malloc(CONFIG_ENV_SIZE_2);
747 memset(buf, 0, CONFIG_ENV_SIZE_2);
748 sprintf(str, "bp_ip=%s", argv[1]);
750 crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
753 if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2,
754 0, (uchar *)buf, CONFIG_ENV_SIZE_2))
755 puts("\nError writing backplane EEPROM!\n");
762 setbpip, 2, 1, do_set_bpip,
763 "Write Backplane IP-Address",
767 #endif /* CONFIG_CPCI405AB */