3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 int board_early_init_f (void)
34 unsigned long CPC0_CR0Reg;
39 CPC0_CR0Reg = mfdcr(CPC0_CR0);
40 mtdcr(CPC0_CR0, CPC0_CR0Reg |
41 ((CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED |
42 CONFIG_SYS_SELF_RST | CONFIG_SYS_INTA_FAKE) << 5));
44 /* set output pins to high */
45 out_be32((void *)GPIO0_OR, CONFIG_SYS_EEPROM_WP);
46 /* setup for output (LED=off) */
47 out_be32((void *)GPIO0_TCR, CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED);
50 * IRQ 0-15 405GP internally generated; active high; level sensitive
51 * IRQ 16 405GP internally generated; active low; level sensitive
53 * IRQ 25 (EXT IRQ 0) PB0; active low; level sensitive
54 * IRQ 26 (EXT IRQ 1) PB1; active low; level sensitive
55 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
56 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
57 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
58 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
59 * IRQ 31 (EXT IRQ 6) unused
61 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
62 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
63 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
64 mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
66 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
67 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
68 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
73 int misc_init_r (void)
75 unsigned long CPC0_CR0Reg;
77 /* adjust flash start and offset */
78 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
79 gd->bd->bi_flashoffset = 0;
82 * Select cts (and not dsr) on uart1
84 CPC0_CR0Reg = mfdcr(CPC0_CR0);
85 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
92 * Check Board Identity:
97 int i = getenv_r ("serial#", str, sizeof(str));
102 puts ("### No HW ID - assuming CPCI2DP");
107 printf(" (Ver 1.0)");
114 #if defined(CONFIG_SYS_EEPROM_WREN)
115 /* Input: <dev_addr> I2C address of EEPROM device to enable.
116 * <state> -1: deliver current state
119 * Returns: -1: wrong device address
120 * 0: dis-/en- able done
121 * 0/1: current state if <state> was -1.
123 int eeprom_write_enable (unsigned dev_addr, int state) {
124 if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
129 /* Enable write access, clear bit GPIO_SINT2. */
130 out_be32((void *)GPIO0_OR,
131 in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
135 /* Disable write access, set bit GPIO_SINT2. */
136 out_be32((void *)GPIO0_OR,
137 in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
141 /* Read current status back. */
142 state = (0 == (in_be32((void *)GPIO0_OR) &
143 CONFIG_SYS_EEPROM_WP));
151 #if defined(CONFIG_SYS_EEPROM_WREN)
152 int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
154 int query = argc == 1;
158 /* Query write access state. */
159 state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
161 puts ("Query of write access state failed.\n");
163 printf ("Write access for device 0x%0x is %sabled.\n",
164 CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
168 if ('0' == argv[1][0]) {
169 /* Disable write access. */
170 state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
172 /* Enable write access. */
173 state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
176 puts ("Setup of write access state failed.\n");
184 eepwren, 2, 0, do_eep_wren,
185 "Enable / disable / query EEPROM write access",
188 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */