2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
30 /* ------------------------------------------------------------------------- */
36 /* fpga configuration data - gzip compressed and generated by bin2c */
37 const unsigned char fpgadata[] =
43 * include common fpga code (for esd boards)
45 #include "../common/fpga.c"
49 int gunzip(void *, int, unsigned char *, int *);
52 int board_pre_init (void)
55 * IRQ 0-15 405GP internally generated; active high; level sensitive
56 * IRQ 16 405GP internally generated; active low; level sensitive
58 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
59 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
60 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
61 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
62 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
63 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
64 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
66 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
67 mtdcr(uicer, 0x00000000); /* disable all ints */
68 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
69 mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
70 mtdcr(uictr, 0x10000000); /* set int trigger levels */
71 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
72 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
75 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
77 mtebc (epcr, 0xa8400000); /* ebc always driven */
83 /* ------------------------------------------------------------------------- */
85 int misc_init_f (void)
87 return 0; /* dummy implementation */
91 int misc_init_r (void)
93 volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
94 volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
95 volatile unsigned char *duart2_mcr = (unsigned char *)((ulong)DUART2_BA + 4);
96 volatile unsigned char *duart3_mcr = (unsigned char *)((ulong)DUART3_BA + 4);
98 ulong len = sizeof(fpgadata);
103 dst = malloc(CFG_FPGA_MAX_SIZE);
104 if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
105 printf ("GUNZIP ERROR - must RESET board to recover\n");
106 do_reset (NULL, 0, 0, NULL);
109 status = fpga_boot(dst, len);
111 printf("\nFPGA: Booting failed ");
113 case ERROR_FPGA_PRG_INIT_LOW:
114 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
116 case ERROR_FPGA_PRG_INIT_HIGH:
117 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
119 case ERROR_FPGA_PRG_DONE:
120 printf("(Timeout: DONE not high after programming FPGA)\n ");
124 /* display infos on fpgaimage */
126 for (i=0; i<4; i++) {
128 printf("FPGA: %s\n", &(dst[index+1]));
133 for (i=20; i>0; i--) {
134 printf("Rebooting in %2d seconds \r",i);
135 for (index=0;index<1000;index++)
139 do_reset(NULL, 0, 0, NULL);
144 /* display infos on fpgaimage */
146 for (i=0; i<4; i++) {
148 printf("%s ", &(dst[index+1]));
156 * Reset FPGA via FPGA_DATA pin
158 SET_FPGA(FPGA_PRG | FPGA_CLK);
159 udelay(1000); /* wait 1ms */
160 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
161 udelay(1000); /* wait 1ms */
164 * Reset external DUARTs
166 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
167 udelay(10); /* wait 10us */
168 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
169 udelay(1000); /* wait 1ms */
172 * Set NAND-FLASH GPIO signals to default
174 out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
175 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
178 * Enable interrupts in exar duart mcr[3]
190 * Check Board Identity:
193 int checkboard (void)
195 unsigned char str[64];
196 int i = getenv_r ("serial#", str, sizeof(str));
201 puts ("### No HW ID - assuming ASH405");
211 /* ------------------------------------------------------------------------- */
213 long int initdram (int board_type)
217 mtdcr(memcfga, mem_mb0cf);
218 val = mfdcr(memcfgd);
221 printf("\nmb0cf=%x\n", val); /* test-only */
222 printf("strap=%x\n", mfdcr(strap)); /* test-only */
225 return (4*1024*1024 << ((val & 0x000e0000) >> 17));
228 /* ------------------------------------------------------------------------- */
232 /* TODO: XXX XXX XXX */
233 printf ("test: 16 MB - ok\n");
238 /* ------------------------------------------------------------------------- */
240 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
241 #include <linux/mtd/nand.h>
242 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
246 nand_probe(CFG_NAND_BASE);
247 if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
249 print_size(nand_dev_desc[0].totlen, "\n");