2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/processor.h>
14 /* ------------------------------------------------------------------------- */
20 extern void lxt971_no_sleep(void);
22 /* fpga configuration data - gzip compressed and generated by bin2c */
23 const unsigned char fpgadata[] =
29 * include common fpga code (for esd boards)
31 #include "../common/fpga.c"
34 int board_early_init_f (void)
37 * IRQ 0-15 405GP internally generated; active high; level sensitive
38 * IRQ 16 405GP internally generated; active low; level sensitive
40 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
41 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
42 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
43 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
44 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
45 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
46 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
48 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
49 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
50 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
51 mtdcr(UIC0PR, 0xFFFFFF9F); /* set int polarities */
52 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
53 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
54 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
57 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
59 mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
64 int misc_init_r (void)
67 ulong len = sizeof(fpgadata);
72 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
73 if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
74 printf ("GUNZIP ERROR - must RESET board to recover\n");
75 do_reset (NULL, 0, 0, NULL);
78 status = fpga_boot(dst, len);
80 printf("\nFPGA: Booting failed ");
82 case ERROR_FPGA_PRG_INIT_LOW:
83 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
85 case ERROR_FPGA_PRG_INIT_HIGH:
86 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
88 case ERROR_FPGA_PRG_DONE:
89 printf("(Timeout: DONE not high after programming FPGA)\n ");
93 /* display infos on fpgaimage */
97 printf("FPGA: %s\n", &(dst[index+1]));
102 for (i=20; i>0; i--) {
103 printf("Rebooting in %2d seconds \r",i);
104 for (index=0;index<1000;index++)
108 do_reset(NULL, 0, 0, NULL);
113 /* display infos on fpgaimage */
115 for (i=0; i<4; i++) {
117 printf("%s ", &(dst[index+1]));
125 * Reset FPGA via FPGA_DATA pin
127 SET_FPGA(FPGA_PRG | FPGA_CLK);
128 udelay(1000); /* wait 1ms */
129 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
130 udelay(1000); /* wait 1ms */
133 * Reset external DUARTs
135 out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_DUART_RST);
136 udelay(10); /* wait 10us */
137 out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
138 udelay(1000); /* wait 1ms */
141 * Enable interrupts in exar duart mcr[3]
143 out_8((void *)(DUART0_BA + 4), 0x08);
144 out_8((void *)(DUART1_BA + 4), 0x08);
145 out_8((void *)(DUART2_BA + 4), 0x08);
146 out_8((void *)(DUART3_BA + 4), 0x08);
153 * Check Board Identity:
156 int checkboard (void)
159 int i = getenv_f("serial#", str, sizeof(str));
164 puts ("### No HW ID - assuming ASH405");
176 #ifdef CONFIG_LXT971_NO_SLEEP
178 * Disable sleep mode in LXT971