board/engicam/icorem6_rqs/icorem6_rqs.c

   1 /*
   2  * Copyright (C) 2016 Amarula Solutions B.V.
   3  * Copyright (C) 2016 Engicam S.r.l.
   4  * Author: Jagan Teki <jagan@amarulasolutions.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10
  11 #include <asm/io.h>
  12 #include <asm/gpio.h>
  13 #include <linux/sizes.h>
  14
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/crm_regs.h>
  17 #include <asm/arch/iomux.h>
  18 #include <asm/arch/mx6-pins.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/imx-common/iomux-v3.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  25         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  26         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  27
  28 static iomux_v3_cfg_t const uart4_pads[] = {
  29         IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  30         IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  31 };
  32
  33 int board_early_init_f(void)
  34 {
  35         SETUP_IOMUX_PADS(uart4_pads);
  36
  37         return 0;
  38 }
  39
  40 int board_init(void)
  41 {
  42         /* Address of boot parameters */
  43         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  44
  45         return 0;
  46 }
  47
  48 int dram_init(void)
  49 {
  50         gd->ram_size = imx_ddr_size();
  51
  52         return 0;
  53 }
  54
  55 #ifdef CONFIG_SPL_BUILD
  56 #include <libfdt.h>
  57 #include <spl.h>
  58
  59 #include <asm/arch/crm_regs.h>
  60 #include <asm/arch/mx6-ddr.h>
  61
  62 /* MMC board initialization is needed till adding DM support in SPL */
  63 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
  64 #include <mmc.h>
  65 #include <fsl_esdhc.h>
  66
  67 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  68         PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_HIGH |               \
  69         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  70
  71 static iomux_v3_cfg_t const usdhc3_pads[] = {
  72         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  73         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  74         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  75         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  76         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  77         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  78 };
  79
  80 struct fsl_esdhc_cfg usdhc_cfg[1] = {
  81         {USDHC3_BASE_ADDR, 1, 4},
  82 };
  83
  84 int board_mmc_getcd(struct mmc *mmc)
  85 {
  86         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  87         int ret = 0;
  88
  89         switch (cfg->esdhc_base) {
  90         case USDHC3_BASE_ADDR:
  91                 ret = 1;
  92                 break;
  93         }
  94
  95         return ret;
  96 }
  97
  98 int board_mmc_init(bd_t *bis)
  99 {
 100         int i, ret;
 101
 102         /*
 103         * According to the board_mmc_init() the following map is done:
 104         * (U-boot device node)    (Physical Port)
 105         * mmc0                          USDHC3
 106         */
 107         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 108                 switch (i) {
 109                 case 0:
 110                         SETUP_IOMUX_PADS(usdhc3_pads);
 111                         usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 112                         break;
 113                 default:
 114                         printf("Warning - USDHC%d controller not supporting\n",
 115                                i + 1);
 116                         return 0;
 117                 }
 118
 119                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 120                 if (ret) {
 121                         printf("Warning: failed to initialize mmc dev %d\n", i);
 122                         return ret;
 123                 }
 124         }
 125
 126         return 0;
 127 }
 128 #endif
 129
 130 /*
 131  * Driving strength:
 132  *   0x30 == 40 Ohm
 133  *   0x28 == 48 Ohm
 134  */
 135
 136 #define IMX6DQ_DRIVE_STRENGTH           0x30
 137 #define IMX6SDL_DRIVE_STRENGTH          0x28
 138
 139 /* configure MX6Q/DUAL mmdc DDR io registers */
 140 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
 141         .dram_sdqs0 = 0x28,
 142         .dram_sdqs1 = 0x28,
 143         .dram_sdqs2 = 0x28,
 144         .dram_sdqs3 = 0x28,
 145         .dram_sdqs4 = 0x28,
 146         .dram_sdqs5 = 0x28,
 147         .dram_sdqs6 = 0x28,
 148         .dram_sdqs7 = 0x28,
 149         .dram_dqm0 = 0x28,
 150         .dram_dqm1 = 0x28,
 151         .dram_dqm2 = 0x28,
 152         .dram_dqm3 = 0x28,
 153         .dram_dqm4 = 0x28,
 154         .dram_dqm5 = 0x28,
 155         .dram_dqm6 = 0x28,
 156         .dram_dqm7 = 0x28,
 157         .dram_cas = 0x30,
 158         .dram_ras = 0x30,
 159         .dram_sdclk_0 = 0x30,
 160         .dram_sdclk_1 = 0x30,
 161         .dram_reset = 0x30,
 162         .dram_sdcke0 = 0x3000,
 163         .dram_sdcke1 = 0x3000,
 164         .dram_sdba2 = 0x00000000,
 165         .dram_sdodt0 = 0x30,
 166         .dram_sdodt1 = 0x30,
 167 };
 168
 169 /* configure MX6Q/DUAL mmdc GRP io registers */
 170 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
 171         .grp_b0ds = 0x30,
 172         .grp_b1ds = 0x30,
 173         .grp_b2ds = 0x30,
 174         .grp_b3ds = 0x30,
 175         .grp_b4ds = 0x30,
 176         .grp_b5ds = 0x30,
 177         .grp_b6ds = 0x30,
 178         .grp_b7ds = 0x30,
 179         .grp_addds = 0x30,
 180         .grp_ddrmode_ctl = 0x00020000,
 181         .grp_ddrpke = 0x00000000,
 182         .grp_ddrmode = 0x00020000,
 183         .grp_ctlds = 0x30,
 184         .grp_ddr_type = 0x000c0000,
 185 };
 186
 187 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
 188 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
 189         .dram_sdclk_0 = 0x30,
 190         .dram_sdclk_1 = 0x30,
 191         .dram_cas = 0x30,
 192         .dram_ras = 0x30,
 193         .dram_reset = 0x30,
 194         .dram_sdcke0 = 0x30,
 195         .dram_sdcke1 = 0x30,
 196         .dram_sdba2 = 0x00000000,
 197         .dram_sdodt0 = 0x30,
 198         .dram_sdodt1 = 0x30,
 199         .dram_sdqs0 = 0x28,
 200         .dram_sdqs1 = 0x28,
 201         .dram_sdqs2 = 0x28,
 202         .dram_sdqs3 = 0x28,
 203         .dram_sdqs4 = 0x28,
 204         .dram_sdqs5 = 0x28,
 205         .dram_sdqs6 = 0x28,
 206         .dram_sdqs7 = 0x28,
 207         .dram_dqm0 = 0x28,
 208         .dram_dqm1 = 0x28,
 209         .dram_dqm2 = 0x28,
 210         .dram_dqm3 = 0x28,
 211         .dram_dqm4 = 0x28,
 212         .dram_dqm5 = 0x28,
 213         .dram_dqm6 = 0x28,
 214         .dram_dqm7 = 0x28,
 215 };
 216
 217 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
 218 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 219         .grp_ddr_type = 0x000c0000,
 220         .grp_ddrmode_ctl = 0x00020000,
 221         .grp_ddrpke = 0x00000000,
 222         .grp_addds = 0x30,
 223         .grp_ctlds = 0x30,
 224         .grp_ddrmode = 0x00020000,
 225         .grp_b0ds = 0x28,
 226         .grp_b1ds = 0x28,
 227         .grp_b2ds = 0x28,
 228         .grp_b3ds = 0x28,
 229         .grp_b4ds = 0x28,
 230         .grp_b5ds = 0x28,
 231         .grp_b6ds = 0x28,
 232         .grp_b7ds = 0x28,
 233 };
 234
 235 /* mt41j256 */
 236 static struct mx6_ddr3_cfg mt41j256 = {
 237         .mem_speed = 1066,
 238         .density = 2,
 239         .width = 16,
 240         .banks = 8,
 241         .rowaddr = 13,
 242         .coladdr = 10,
 243         .pagesz = 2,
 244         .trcd = 1375,
 245         .trcmin = 4875,
 246         .trasmin = 3500,
 247         .SRT = 0,
 248 };
 249
 250 static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
 251         .p0_mpwldectrl0 = 0x000E0009,
 252         .p0_mpwldectrl1 = 0x0018000E,
 253         .p1_mpwldectrl0 = 0x00000007,
 254         .p1_mpwldectrl1 = 0x00000000,
 255         .p0_mpdgctrl0 = 0x43280334,
 256         .p0_mpdgctrl1 = 0x031C0314,
 257         .p1_mpdgctrl0 = 0x4318031C,
 258         .p1_mpdgctrl1 = 0x030C0258,
 259         .p0_mprddlctl = 0x3E343A40,
 260         .p1_mprddlctl = 0x383C3844,
 261         .p0_mpwrdlctl = 0x40404440,
 262         .p1_mpwrdlctl = 0x4C3E4446,
 263 };
 264
 265 /* DDR 64bit */
 266 static struct mx6_ddr_sysinfo mem_q = {
 267         .ddr_type       = DDR_TYPE_DDR3,
 268         .dsize          = 2,
 269         .cs1_mirror     = 0,
 270         /* config for full 4GB range so that get_mem_size() works */
 271         .cs_density     = 32,
 272         .ncs            = 1,
 273         .bi_on          = 1,
 274         .rtt_nom        = 2,
 275         .rtt_wr         = 2,
 276         .ralat          = 5,
 277         .walat          = 0,
 278         .mif3_mode      = 3,
 279         .rst_to_cke     = 0x23,
 280         .sde_to_rst     = 0x10,
 281 };
 282
 283 static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
 284         .p0_mpwldectrl0 = 0x001F0024,
 285         .p0_mpwldectrl1 = 0x00110018,
 286         .p1_mpwldectrl0 = 0x001F0024,
 287         .p1_mpwldectrl1 = 0x00110018,
 288         .p0_mpdgctrl0 = 0x4230022C,
 289         .p0_mpdgctrl1 = 0x02180220,
 290         .p1_mpdgctrl0 = 0x42440248,
 291         .p1_mpdgctrl1 = 0x02300238,
 292         .p0_mprddlctl = 0x44444A48,
 293         .p1_mprddlctl = 0x46484A42,
 294         .p0_mpwrdlctl = 0x38383234,
 295         .p1_mpwrdlctl = 0x3C34362E,
 296 };
 297
 298 /* DDR 64bit 1GB */
 299 static struct mx6_ddr_sysinfo mem_dl = {
 300         .dsize          = 2,
 301         .cs1_mirror     = 0,
 302         /* config for full 4GB range so that get_mem_size() works */
 303         .cs_density     = 32,
 304         .ncs            = 1,
 305         .bi_on          = 1,
 306         .rtt_nom        = 1,
 307         .rtt_wr         = 1,
 308         .ralat          = 5,
 309         .walat          = 0,
 310         .mif3_mode      = 3,
 311         .rst_to_cke     = 0x23,
 312         .sde_to_rst     = 0x10,
 313 };
 314
 315 /* DDR 32bit 512MB */
 316 static struct mx6_ddr_sysinfo mem_s = {
 317         .dsize          = 1,
 318         .cs1_mirror     = 0,
 319         /* config for full 4GB range so that get_mem_size() works */
 320         .cs_density     = 32,
 321         .ncs            = 1,
 322         .bi_on          = 1,
 323         .rtt_nom        = 1,
 324         .rtt_wr         = 1,
 325         .ralat          = 5,
 326         .walat          = 0,
 327         .mif3_mode      = 3,
 328         .rst_to_cke     = 0x23,
 329         .sde_to_rst     = 0x10,
 330 };
 331
 332 static void ccgr_init(void)
 333 {
 334         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 335
 336         writel(0x00003F3F, &ccm->CCGR0);
 337         writel(0x0030FC00, &ccm->CCGR1);
 338         writel(0x000FC000, &ccm->CCGR2);
 339         writel(0x3F300000, &ccm->CCGR3);
 340         writel(0xFF00F300, &ccm->CCGR4);
 341         writel(0x0F0000C3, &ccm->CCGR5);
 342         writel(0x000003CC, &ccm->CCGR6);
 343 }
 344
 345 static void gpr_init(void)
 346 {
 347         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 348
 349         /* enable AXI cache for VDOA/VPU/IPU */
 350         writel(0xF00000CF, &iomux->gpr[4]);
 351         /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
 352         writel(0x007F007F, &iomux->gpr[6]);
 353         writel(0x007F007F, &iomux->gpr[7]);
 354 }
 355
 356 static void spl_dram_init(void)
 357 {
 358         if (is_mx6solo()) {
 359                 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 360                 mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
 361         } else if (is_mx6dl()) {
 362                 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 363                 mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
 364         } else if (is_mx6dq()) {
 365                 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
 366                 mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
 367         }
 368
 369         udelay(100);
 370 }
 371
 372 void board_init_f(ulong dummy)
 373 {
 374         ccgr_init();
 375
 376         /* setup AIPS and disable watchdog */
 377         arch_cpu_init();
 378
 379         gpr_init();
 380
 381         /* iomux */
 382         board_early_init_f();
 383
 384         /* setup GP timer */
 385         timer_init();
 386
 387         /* UART clocks enabled and gd valid - init serial console */
 388         preloader_console_init();
 389
 390         /* DDR initialization */
 391         spl_dram_init();
 392
 393         /* Clear the BSS. */
 394         memset(__bss_start, 0, __bss_end - __bss_start);
 395
 396         /* load/boot image from boot device */
 397         board_init_r(NULL, 0);
 398 }
 399 #endif