2 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
6 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/sizes.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/iomux.h>
17 #include <asm/arch/mx6-pins.h>
18 #include <asm/arch/sys_proto.h>
19 #include <asm/imx-common/iomux-v3.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
24 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
25 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
27 static iomux_v3_cfg_t const uart1_pads[] = {
28 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
29 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
32 int board_early_init_f(void)
34 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
41 /* Address of boot parameters */
42 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
49 gd->ram_size = imx_ddr_size();
54 #ifdef CONFIG_SPL_BUILD
58 #include <asm/arch/crm_regs.h>
59 #include <asm/arch/mx6-ddr.h>
61 /* MMC board initialization is needed till adding DM support in SPL */
62 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
64 #include <fsl_esdhc.h>
66 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
67 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
68 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
70 static iomux_v3_cfg_t const usdhc1_pads[] = {
71 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
72 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
73 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
74 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
75 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
76 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
79 MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
81 MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
83 MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
86 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
88 struct fsl_esdhc_cfg usdhc_cfg[1] = {
89 {USDHC1_BASE_ADDR, 0, 4},
92 int board_mmc_getcd(struct mmc *mmc)
94 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
97 switch (cfg->esdhc_base) {
98 case USDHC1_BASE_ADDR:
99 ret = !gpio_get_value(USDHC1_CD_GPIO);
106 int board_mmc_init(bd_t *bis)
111 * According to the board_mmc_init() the following map is done:
112 * (U-boot device node) (Physical Port)
115 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
118 imx_iomux_v3_setup_multiple_pads(
119 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
120 gpio_direction_input(USDHC1_CD_GPIO);
121 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
124 printf("Warning - USDHC%d controller not supporting\n",
129 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
131 printf("Warning: failed to initialize mmc dev %d\n", i);
138 #endif /* CONFIG_FSL_ESDHC */
140 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
141 .grp_addds = 0x00000030,
142 .grp_ddrmode_ctl = 0x00020000,
143 .grp_b0ds = 0x00000030,
144 .grp_ctlds = 0x00000030,
145 .grp_b1ds = 0x00000030,
146 .grp_ddrpke = 0x00000000,
147 .grp_ddrmode = 0x00020000,
148 .grp_ddr_type = 0x000c0000,
151 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
152 .dram_dqm0 = 0x00000030,
153 .dram_dqm1 = 0x00000030,
154 .dram_ras = 0x00000030,
155 .dram_cas = 0x00000030,
156 .dram_odt0 = 0x00000030,
157 .dram_odt1 = 0x00000030,
158 .dram_sdba2 = 0x00000000,
159 .dram_sdclk_0 = 0x00000008,
160 .dram_sdqs0 = 0x00000038,
161 .dram_sdqs1 = 0x00000030,
162 .dram_reset = 0x00000030,
165 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
166 .p0_mpwldectrl0 = 0x00070007,
167 .p0_mpdgctrl0 = 0x41490145,
168 .p0_mprddlctl = 0x40404546,
169 .p0_mpwrdlctl = 0x4040524D,
172 struct mx6_ddr_sysinfo ddr_sysinfo = {
178 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
179 .walat = 1, /* Write additional latency */
180 .ralat = 5, /* Read additional latency */
181 .mif3_mode = 3, /* Command prediction working mode */
182 .bi_on = 1, /* Bank interleaving enabled */
183 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
184 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
185 .ddr_type = DDR_TYPE_DDR3,
188 static struct mx6_ddr3_cfg mem_ddr = {
201 static void ccgr_init(void)
203 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
205 writel(0xFFFFFFFF, &ccm->CCGR0);
206 writel(0xFFFFFFFF, &ccm->CCGR1);
207 writel(0xFFFFFFFF, &ccm->CCGR2);
208 writel(0xFFFFFFFF, &ccm->CCGR3);
209 writel(0xFFFFFFFF, &ccm->CCGR4);
210 writel(0xFFFFFFFF, &ccm->CCGR5);
211 writel(0xFFFFFFFF, &ccm->CCGR6);
212 writel(0xFFFFFFFF, &ccm->CCGR7);
215 static void spl_dram_init(void)
217 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
218 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
221 void board_init_f(ulong dummy)
223 /* setup AIPS and disable watchdog */
228 /* iomux and setup of i2c */
229 board_early_init_f();
234 /* UART clocks enabled and gd valid - init serial console */
235 preloader_console_init();
237 /* DDR initialization */
241 memset(__bss_start, 0, __bss_end - __bss_start);
243 /* load/boot image from boot device */
244 board_init_r(NULL, 0);
246 #endif /* CONFIG_SPL_BUILD */