3 * EMK Elektronik GmbH <www.emk-elektronik.de>
4 * Reinhard Meyer <r.meyer@emk-elektronik.de>
6 * Board specific routines for the TOP860
9 * - interface to VPD data (mac address, clock speeds)
11 * - serial io initialisation
12 * - ethernet io initialisation
14 * -----------------------------------------------------------------
15 * See file CREDITS for list of people who contributed to this
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
39 /*****************************************************************************
40 * UPM table for 60ns EDO RAM at 25 MHz bus/external clock
41 *****************************************************************************/
42 static const uint edo_60ns_25MHz_tbl[] = {
44 /* single read (offset 0x00 in upm ram) */
45 0x0ff3fc04,0x08f3fc04,0x00f3fc04,0x00f3fc00,
46 0x33f7fc07,0xfffffc05,0xfffffc05,0xfffffc05,
47 /* burst read (offset 0x08 in upm ram) */
48 0x0ff3fc04,0x08f3fc04,0x00f3fc0c,0x0ff3fc40,
49 0x0cf3fc04,0x03f3fc48,0x0cf3fc04,0x03f3fc48,
50 0x0cf3fc04,0x03f3fc00,0x3ff7fc07,0xfffffc05,
51 0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,
52 /* single write (offset 0x18 in upm ram) */
53 0x0ffffc04,0x08fffc04,0x30fffc00,0xf1fffc07,
54 0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,
55 /* burst write (offset 0x20 in upm ram) */
56 0x0ffffc04,0x08fffc00,0x00fffc04,0x03fffc4c,
57 0x00fffc00,0x07fffc4c,0x00fffc00,0x0ffffc4c,
58 0x00fffc00,0x3ffffc07,0xfffffc05,0xfffffc05,
59 0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,
60 /* refresh (offset 0x30 in upm ram) */
61 0xc0fffc04,0x07fffc04,0x0ffffc04,0x0ffffc04,
62 0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,
63 0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,
64 /* exception (offset 0x3C in upm ram) */
65 0xfffffc07,0xfffffc03,0xfffffc05,0xfffffc05,
68 /*****************************************************************************
69 * Print Board Identity
70 *****************************************************************************/
73 puts ("Board:"CONFIG_IDENT_STRING"\n");
77 /*****************************************************************************
78 * Initialize DRAM controller
79 *****************************************************************************/
80 phys_size_t initdram (int board_type)
82 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
83 volatile memctl8xx_t *memctl = &immap->im_memctl;
86 * Only initialize memory controller when running from FLASH.
87 * When running from RAM, don't touch it.
89 if ((ulong) initdram & 0xff000000) {
90 volatile uint *addr1, *addr2;
93 upmconfig (UPMA, (uint *) edo_60ns_25MHz_tbl,
94 sizeof (edo_60ns_25MHz_tbl) / sizeof (uint));
95 memctl->memc_mptpr = 0x0200;
96 memctl->memc_mamr = 0x0ca20330;
97 memctl->memc_or2 = -CONFIG_SYS_DRAM_MAX | OR_CSNT_SAM;
98 memctl->memc_br2 = CONFIG_SYS_DRAM_BASE | BR_MS_UPMA | BR_V;
100 * Do 8 read accesses to DRAM
102 addr1 = (volatile uint *) 0;
103 addr2 = (volatile uint *) 0x00400000;
104 for (i = 0; i < 8; i++)
108 * Now check whether we got 4MB or 16MB populated
110 addr1[0] = 0x12345678;
111 addr1[1] = 0x9abcdef0;
112 addr2[0] = 0xfeedc0de;
113 addr2[1] = 0x47110815;
114 if (addr1[0] == 0xfeedc0de && addr1[1] == 0x47110815) {
115 /* only 4MB populated */
116 memctl->memc_or2 = -(CONFIG_SYS_DRAM_MAX / 4) | OR_CSNT_SAM;
120 return -(memctl->memc_or2 & 0xffff0000);
123 /*****************************************************************************
124 * prepare for FLASH detection
125 *****************************************************************************/
126 void flash_preinit(void)
130 /*****************************************************************************
131 * finalize FLASH setup
132 *****************************************************************************/
133 void flash_afterinit(uint bank, ulong start, ulong size)
137 /*****************************************************************************
138 * otherinits after RAM is there and we are relocated to RAM
139 * note: though this is an int function, nobody cares for the result!
140 *****************************************************************************/
141 int misc_init_r (void)
143 /* read 'factory' part of EEPROM */
144 extern void read_factory_r (void);