3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 /*****************************************************************************
32 * initialize SDRAM/DDRAM controller.
33 * TBD: get data from I2C EEPROM
34 *****************************************************************************/
35 long int initdram (int board_type)
44 #define MODE_EN 0x80000000
48 /* configure SDRAM start/end */
49 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = (CFG_SDRAM_BASE & 0xFFF00000) | CFG_DRAM_RAM_SIZE;
50 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
52 /* setup config registers */
53 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = CFG_DRAM_CONFIG1;
54 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = CFG_DRAM_CONFIG2;
56 /* unlock mode register */
57 *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN;
58 /* precharge all banks */
59 *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_PRE;
61 /* set extended mode register */
62 *(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_EMODE;
64 /* set mode register */
65 *(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_MODE | 0x0400;
66 /* precharge all banks */
67 *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_PRE;
69 *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_REF;
70 /* set mode register */
71 *(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_MODE;
72 /* normal operation */
73 *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL;
74 /* write default TAP delay */
75 *(vu_long *)MPC5XXX_CDM_PORCFG = CFG_DRAM_TAP_DEL << 24;
78 for (tap_del = 0; tap_del < 32; tap_del++)
80 *(vu_long *)MPC5XXX_CDM_PORCFG = tap_del << 24;
82 printf ("\nTAP Delay:%x Filling DRAM...", *(vu_long *)MPC5XXX_CDM_PORCFG);
83 for (t = 0; t < 0x04000000; t+=4)
85 printf ("Checking DRAM...\n");
86 for (t = 0; t < 0x04000000; t+=4)
88 ulong rval = *(vu_long *) t;
91 printf ("mismatch at %x: ", t);
92 printf (" 1.read %x", rval);
93 printf (" 2.read %x", *(vu_long *) t);
94 printf (" 3.read %x", *(vu_long *) t);
100 #endif /* CFG_RAMBOOT */
102 dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20);
104 /* return total ram size */
108 /*****************************************************************************
109 * print board identification
110 *****************************************************************************/
111 int checkboard (void)
113 #if defined (CONFIG_EVAL5200)
114 puts ("Board: EMK TOP5200 on EVAL5200\n");
116 #if defined (CONFIG_LITE5200)
117 puts ("Board: LITE5200\n");
119 #if defined (CONFIG_MINI5200)
120 puts ("Board: EMK TOP5200 on MINI5200\n");
122 puts ("Board: EMK TOP5200\n");
129 /*****************************************************************************
130 * prepare for FLASH detection
131 *****************************************************************************/
132 void flash_preinit(void)
135 * Now, when we are in RAM, enable flash write
136 * access for detection process.
137 * Note that CS_BOOT cannot be cleared when
138 * executing in flash.
140 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
143 /*****************************************************************************
144 * finalize FLASH setup
145 *****************************************************************************/
146 void flash_afterinit(uint bank, ulong start, ulong size)
148 if (bank == 0) { /* adjust mapping */
149 *(vu_long *)MPC5XXX_BOOTCS_START =
150 *(vu_long *)MPC5XXX_CS0_START = START_REG(start);
151 *(vu_long *)MPC5XXX_BOOTCS_STOP =
152 *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(start, size);
156 /*****************************************************************************
157 * otherinits after RAM is there and we are relocated to RAM
158 * note: though this is an int function, nobody cares for the result!
159 *****************************************************************************/
160 int misc_init_r (void)
162 #if !defined (CONFIG_LITE5200)
163 /* read 'factory' part of EEPROM */
164 extern void read_factory_r (void);
170 /*****************************************************************************
171 * initialize the PCI system
172 *****************************************************************************/
174 static struct pci_controller hose;
176 extern void pci_mpc5xxx_init(struct pci_controller *);
178 void pci_init_board(void)
180 pci_mpc5xxx_init(&hose);
184 /*****************************************************************************
185 * provide the IDE Reset Function
186 *****************************************************************************/
187 #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
189 void init_ide_reset (void)
191 debug ("init_ide_reset\n");
193 /* Configure PSC1_4 as GPIO output for ATA reset */
194 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
195 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
198 void ide_set_reset (int idereset)
200 debug ("ide_reset(%d)\n", idereset);
203 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
205 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
208 #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */