board/efikamx/efikamx.c

   1 /*
   2  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   3  *
   4  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/io.h>
  27 #include <asm/arch/imx-regs.h>
  28 #include <asm/arch/mx5x_pins.h>
  29 #include <asm/arch/iomux.h>
  30 #include <asm/gpio.h>
  31 #include <asm/errno.h>
  32 #include <asm/arch/sys_proto.h>
  33 #include <asm/arch/crm_regs.h>
  34 #include <i2c.h>
  35 #include <mmc.h>
  36 #include <fsl_esdhc.h>
  37 #include <fsl_pmic.h>
  38 #include <mc13892.h>
  39
  40 DECLARE_GLOBAL_DATA_PTR;
  41
  42 /*
  43  * Compile-time error checking
  44  */
  45 #ifndef CONFIG_MXC_SPI
  46 #error "CONFIG_MXC_SPI not set, this is essential for board's operation!"
  47 #endif
  48
  49 /*
  50  * Shared variables / local defines
  51  */
  52 /* LED */
  53 #define EFIKAMX_LED_BLUE        0x1
  54 #define EFIKAMX_LED_GREEN       0x2
  55 #define EFIKAMX_LED_RED         0x4
  56
  57 void efikamx_toggle_led(uint32_t mask);
  58
  59 /* Board revisions */
  60 #define EFIKAMX_BOARD_REV_11    0x1
  61 #define EFIKAMX_BOARD_REV_12    0x2
  62 #define EFIKAMX_BOARD_REV_13    0x3
  63 #define EFIKAMX_BOARD_REV_14    0x4
  64
  65 #define EFIKASB_BOARD_REV_13    0x1
  66 #define EFIKASB_BOARD_REV_20    0x2
  67
  68 /*
  69  * Board identification
  70  */
  71 u32 get_efikamx_rev(void)
  72 {
  73         u32 rev = 0;
  74         /*
  75          * Retrieve board ID:
  76          *      rev1.1: 1,1,1
  77          *      rev1.2: 1,1,0
  78          *      rev1.3: 1,0,1
  79          *      rev1.4: 1,0,0
  80          */
  81         mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
  82         /* set to 1 in order to get correct value on board rev1.1 */
  83         gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), 1);
  84
  85         mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
  86         mxc_iomux_set_pad(MX51_PIN_NANDF_CS0, PAD_CTL_100K_PU);
  87         gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0));
  88         rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0))) << 0;
  89
  90         mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_GPIO);
  91         mxc_iomux_set_pad(MX51_PIN_NANDF_CS1, PAD_CTL_100K_PU);
  92         gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1));
  93         rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1))) << 1;
  94
  95         mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_GPIO);
  96         mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, PAD_CTL_100K_PU);
  97         gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3));
  98         rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3))) << 2;
  99
 100         return (~rev & 0x7) + 1;
 101 }
 102
 103 inline u32 get_efikasb_rev(void)
 104 {
 105         u32 rev = 0;
 106
 107         mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_GPIO);
 108         mxc_iomux_set_pad(MX51_PIN_EIM_CS3, PAD_CTL_100K_PU);
 109         gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3));
 110         rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3))) << 0;
 111
 112         mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_GPIO);
 113         mxc_iomux_set_pad(MX51_PIN_EIM_CS4, PAD_CTL_100K_PU);
 114         gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_EIM_CS4));
 115         rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS4))) << 1;
 116
 117         return rev;
 118 }
 119
 120 inline uint32_t get_efika_rev(void)
 121 {
 122         if (machine_is_efikamx())
 123                 return get_efikamx_rev();
 124         else
 125                 return get_efikasb_rev();
 126 }
 127
 128 u32 get_board_rev(void)
 129 {
 130         return get_cpu_rev() | (get_efika_rev() << 8);
 131 }
 132
 133 /*
 134  * DRAM initialization
 135  */
 136 int dram_init(void)
 137 {
 138         /* dram_init must store complete ramsize in gd->ram_size */
 139         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 140                                 PHYS_SDRAM_1_SIZE);
 141         return 0;
 142 }
 143
 144 /*
 145  * UART configuration
 146  */
 147 static void setup_iomux_uart(void)
 148 {
 149         unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
 150                         PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
 151
 152         mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
 153         mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
 154         mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
 155         mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
 156         mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
 157         mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
 158         mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
 159         mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
 160 }
 161
 162 /*
 163  * SPI configuration
 164  */
 165 #ifdef CONFIG_MXC_SPI
 166 static void setup_iomux_spi(void)
 167 {
 168         /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
 169         mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
 170         mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
 171                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 172
 173         /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
 174         mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
 175         mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
 176                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 177
 178         /* Configure SS0 as a GPIO */
 179         mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO);
 180         gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), 0);
 181
 182         /* Configure SS1 as a GPIO */
 183         mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO);
 184         gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 1);
 185
 186         /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
 187         mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
 188         mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY,
 189                 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 190
 191         /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
 192         mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
 193         mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
 194                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 195 }
 196 #else
 197 static inline void setup_iomux_spi(void) { }
 198 #endif
 199
 200 /*
 201  * PMIC configuration
 202  */
 203 #ifdef CONFIG_MXC_SPI
 204 static void power_init(void)
 205 {
 206         unsigned int val;
 207         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
 208
 209         /* Write needed to Power Gate 2 register */
 210         val = pmic_reg_read(REG_POWER_MISC);
 211         val &= ~PWGT2SPIEN;
 212         pmic_reg_write(REG_POWER_MISC, val);
 213
 214         /* Externally powered */
 215         val = pmic_reg_read(REG_CHARGE);
 216         val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
 217         pmic_reg_write(REG_CHARGE, val);
 218
 219         /* power up the system first */
 220         pmic_reg_write(REG_POWER_MISC, PWUP);
 221
 222         /* Set core voltage to 1.1V */
 223         val = pmic_reg_read(REG_SW_0);
 224         val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
 225         pmic_reg_write(REG_SW_0, val);
 226
 227         /* Setup VCC (SW2) to 1.25 */
 228         val = pmic_reg_read(REG_SW_1);
 229         val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
 230         pmic_reg_write(REG_SW_1, val);
 231
 232         /* Setup 1V2_DIG1 (SW3) to 1.25 */
 233         val = pmic_reg_read(REG_SW_2);
 234         val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
 235         pmic_reg_write(REG_SW_2, val);
 236         udelay(50);
 237
 238         /* Raise the core frequency to 800MHz */
 239         writel(0x0, &mxc_ccm->cacrr);
 240
 241         /* Set switchers in Auto in NORMAL mode & STANDBY mode */
 242         /* Setup the switcher mode for SW1 & SW2*/
 243         val = pmic_reg_read(REG_SW_4);
 244         val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
 245                 (SWMODE_MASK << SWMODE2_SHIFT)));
 246         val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
 247                 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
 248         pmic_reg_write(REG_SW_4, val);
 249
 250         /* Setup the switcher mode for SW3 & SW4 */
 251         val = pmic_reg_read(REG_SW_5);
 252         val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
 253                 (SWMODE_MASK << SWMODE4_SHIFT)));
 254         val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
 255                 (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
 256         pmic_reg_write(REG_SW_5, val);
 257
 258         /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
 259         val = pmic_reg_read(REG_SETTING_0);
 260         val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
 261         val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
 262         pmic_reg_write(REG_SETTING_0, val);
 263
 264         /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
 265         val = pmic_reg_read(REG_SETTING_1);
 266         val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
 267         val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
 268         pmic_reg_write(REG_SETTING_1, val);
 269
 270         /* Configure VGEN3 and VCAM regulators to use external PNP */
 271         val = VGEN3CONFIG | VCAMCONFIG;
 272         pmic_reg_write(REG_MODE_1, val);
 273         udelay(200);
 274
 275         /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
 276         val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
 277                 VVIDEOEN | VAUDIOEN  | VSDEN;
 278         pmic_reg_write(REG_MODE_1, val);
 279
 280         val = pmic_reg_read(REG_POWER_CTL2);
 281         val |= WDIRESET;
 282         pmic_reg_write(REG_POWER_CTL2, val);
 283
 284         udelay(2500);
 285 }
 286 #else
 287 static inline void power_init(void) { }
 288 #endif
 289
 290 /*
 291  * MMC configuration
 292  */
 293 #ifdef CONFIG_FSL_ESDHC
 294 struct fsl_esdhc_cfg esdhc_cfg[2] = {
 295         {MMC_SDHC1_BASE_ADDR, 1},
 296         {MMC_SDHC2_BASE_ADDR, 1},
 297 };
 298
 299 static inline uint32_t efika_mmc_cd(void)
 300 {
 301         if (machine_is_efikamx())
 302                 return MX51_PIN_GPIO1_0;
 303         else
 304                 return MX51_PIN_EIM_CS2;
 305 }
 306
 307 int board_mmc_getcd(u8 *absent, struct mmc *mmc)
 308 {
 309         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 310         uint32_t cd = efika_mmc_cd();
 311
 312         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
 313                 *absent = gpio_get_value(IOMUX_TO_GPIO(cd));
 314         else
 315                 *absent = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8));
 316
 317         return 0;
 318 }
 319
 320 int board_mmc_init(bd_t *bis)
 321 {
 322         int ret;
 323         uint32_t cd = efika_mmc_cd();
 324
 325         /* SDHC1 is used on all revisions, setup control pins first */
 326         mxc_request_iomux(cd,
 327                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 328         mxc_iomux_set_pad(cd,
 329                 PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
 330                 PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |
 331                 PAD_CTL_ODE_OPENDRAIN_NONE |
 332                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 333         mxc_request_iomux(MX51_PIN_GPIO1_1,
 334                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 335         mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
 336                 PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
 337                 PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
 338                 PAD_CTL_SRE_FAST);
 339
 340         gpio_direction_input(IOMUX_TO_GPIO(cd));
 341         gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1));
 342
 343         /* Internal SDHC1 IOMUX + SDHC2 IOMUX on old boards */
 344         if (machine_is_efikasb() || (machine_is_efikamx() &&
 345                 (get_efika_rev() < EFIKAMX_BOARD_REV_12))) {
 346                 /* SDHC1 IOMUX */
 347                 mxc_request_iomux(MX51_PIN_SD1_CMD,
 348                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 349                 mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
 350                         PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
 351                         PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
 352
 353                 mxc_request_iomux(MX51_PIN_SD1_CLK,
 354                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 355                 mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
 356                         PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
 357                         PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
 358
 359                 mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
 360                 mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
 361                         PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
 362                         PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
 363
 364                 mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
 365                 mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
 366                         PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
 367                         PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
 368
 369                 mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
 370                 mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
 371                         PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
 372                         PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
 373
 374                 mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
 375                 mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
 376                         PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
 377                         PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
 378
 379                 /* SDHC2 IOMUX */
 380                 mxc_request_iomux(MX51_PIN_SD2_CMD,
 381                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 382                 mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
 383                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 384
 385                 mxc_request_iomux(MX51_PIN_SD2_CLK,
 386                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 387                 mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
 388                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 389
 390                 mxc_request_iomux(MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0);
 391                 mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
 392                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 393
 394                 mxc_request_iomux(MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0);
 395                 mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
 396                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 397
 398                 mxc_request_iomux(MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0);
 399                 mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
 400                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 401
 402                 mxc_request_iomux(MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0);
 403                 mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
 404                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 405
 406                 /* SDHC2 Control lines IOMUX */
 407                 mxc_request_iomux(MX51_PIN_GPIO1_7,
 408                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 409                 mxc_iomux_set_pad(MX51_PIN_GPIO1_7,
 410                         PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
 411                         PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |
 412                         PAD_CTL_ODE_OPENDRAIN_NONE |
 413                         PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 414                 mxc_request_iomux(MX51_PIN_GPIO1_8,
 415                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 416                 mxc_iomux_set_pad(MX51_PIN_GPIO1_8,
 417                         PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
 418                         PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
 419                         PAD_CTL_SRE_FAST);
 420
 421                 gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8));
 422                 gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7));
 423
 424                 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 425                 if (!ret)
 426                         ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);
 427         } else {        /* New boards use only SDHC1 */
 428                 /* SDHC1 IOMUX */
 429                 mxc_request_iomux(MX51_PIN_SD1_CMD,
 430                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 431                 mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
 432                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 433
 434                 mxc_request_iomux(MX51_PIN_SD1_CLK,
 435                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 436                 mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
 437                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 438
 439                 mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
 440                 mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
 441                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 442
 443                 mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
 444                 mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
 445                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 446
 447                 mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
 448                 mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
 449                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 450
 451                 mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
 452                 mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
 453                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 454
 455                 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 456         }
 457
 458         return ret;
 459 }
 460 #endif
 461
 462 /*
 463  * ATA
 464  */
 465 #ifdef  CONFIG_MX51_PATA
 466 #define ATA_PAD_CONFIG  (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH)
 467 void setup_iomux_ata(void)
 468 {
 469         mxc_request_iomux(MX51_PIN_NANDF_ALE, IOMUX_CONFIG_ALT1);
 470         mxc_iomux_set_pad(MX51_PIN_NANDF_ALE, ATA_PAD_CONFIG);
 471         mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT1);
 472         mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, ATA_PAD_CONFIG);
 473         mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT1);
 474         mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, ATA_PAD_CONFIG);
 475         mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT1);
 476         mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, ATA_PAD_CONFIG);
 477         mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT1);
 478         mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, ATA_PAD_CONFIG);
 479         mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT1);
 480         mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, ATA_PAD_CONFIG);
 481         mxc_request_iomux(MX51_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT1);
 482         mxc_iomux_set_pad(MX51_PIN_NANDF_RE_B, ATA_PAD_CONFIG);
 483         mxc_request_iomux(MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT1);
 484         mxc_iomux_set_pad(MX51_PIN_NANDF_WE_B, ATA_PAD_CONFIG);
 485         mxc_request_iomux(MX51_PIN_NANDF_CLE, IOMUX_CONFIG_ALT1);
 486         mxc_iomux_set_pad(MX51_PIN_NANDF_CLE, ATA_PAD_CONFIG);
 487         mxc_request_iomux(MX51_PIN_NANDF_RB0, IOMUX_CONFIG_ALT1);
 488         mxc_iomux_set_pad(MX51_PIN_NANDF_RB0, ATA_PAD_CONFIG);
 489         mxc_request_iomux(MX51_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT1);
 490         mxc_iomux_set_pad(MX51_PIN_NANDF_WP_B, ATA_PAD_CONFIG);
 491         mxc_request_iomux(MX51_PIN_GPIO_NAND, IOMUX_CONFIG_ALT1);
 492         mxc_iomux_set_pad(MX51_PIN_GPIO_NAND, ATA_PAD_CONFIG);
 493         mxc_request_iomux(MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT1);
 494         mxc_iomux_set_pad(MX51_PIN_NANDF_RB1, ATA_PAD_CONFIG);
 495         mxc_request_iomux(MX51_PIN_NANDF_D0, IOMUX_CONFIG_ALT1);
 496         mxc_iomux_set_pad(MX51_PIN_NANDF_D0, ATA_PAD_CONFIG);
 497         mxc_request_iomux(MX51_PIN_NANDF_D1, IOMUX_CONFIG_ALT1);
 498         mxc_iomux_set_pad(MX51_PIN_NANDF_D1, ATA_PAD_CONFIG);
 499         mxc_request_iomux(MX51_PIN_NANDF_D2, IOMUX_CONFIG_ALT1);
 500         mxc_iomux_set_pad(MX51_PIN_NANDF_D2, ATA_PAD_CONFIG);
 501         mxc_request_iomux(MX51_PIN_NANDF_D3, IOMUX_CONFIG_ALT1);
 502         mxc_iomux_set_pad(MX51_PIN_NANDF_D3, ATA_PAD_CONFIG);
 503         mxc_request_iomux(MX51_PIN_NANDF_D4, IOMUX_CONFIG_ALT1);
 504         mxc_iomux_set_pad(MX51_PIN_NANDF_D4, ATA_PAD_CONFIG);
 505         mxc_request_iomux(MX51_PIN_NANDF_D5, IOMUX_CONFIG_ALT1);
 506         mxc_iomux_set_pad(MX51_PIN_NANDF_D5, ATA_PAD_CONFIG);
 507         mxc_request_iomux(MX51_PIN_NANDF_D6, IOMUX_CONFIG_ALT1);
 508         mxc_iomux_set_pad(MX51_PIN_NANDF_D6, ATA_PAD_CONFIG);
 509         mxc_request_iomux(MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT1);
 510         mxc_iomux_set_pad(MX51_PIN_NANDF_D7, ATA_PAD_CONFIG);
 511         mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT1);
 512         mxc_iomux_set_pad(MX51_PIN_NANDF_D8, ATA_PAD_CONFIG);
 513         mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT1);
 514         mxc_iomux_set_pad(MX51_PIN_NANDF_D9, ATA_PAD_CONFIG);
 515         mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT1);
 516         mxc_iomux_set_pad(MX51_PIN_NANDF_D10, ATA_PAD_CONFIG);
 517         mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT1);
 518         mxc_iomux_set_pad(MX51_PIN_NANDF_D11, ATA_PAD_CONFIG);
 519         mxc_request_iomux(MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT1);
 520         mxc_iomux_set_pad(MX51_PIN_NANDF_D12, ATA_PAD_CONFIG);
 521         mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT1);
 522         mxc_iomux_set_pad(MX51_PIN_NANDF_D13, ATA_PAD_CONFIG);
 523         mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT1);
 524         mxc_iomux_set_pad(MX51_PIN_NANDF_D14, ATA_PAD_CONFIG);
 525         mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT1);
 526         mxc_iomux_set_pad(MX51_PIN_NANDF_D15, ATA_PAD_CONFIG);
 527 }
 528 #else
 529 static inline void setup_iomux_ata(void) { }
 530 #endif
 531
 532 /*
 533  * LED configuration
 534  */
 535 void setup_iomux_led(void)
 536 {
 537         if (machine_is_efikamx()) {
 538                 /* Blue LED */
 539                 mxc_request_iomux(MX51_PIN_CSI1_D9, IOMUX_CONFIG_ALT3);
 540                 gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), 0);
 541
 542                 /* Green LED */
 543                 mxc_request_iomux(MX51_PIN_CSI1_VSYNC, IOMUX_CONFIG_ALT3);
 544                 gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), 0);
 545
 546                 /* Red LED */
 547                 mxc_request_iomux(MX51_PIN_CSI1_HSYNC, IOMUX_CONFIG_ALT3);
 548                 gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), 0);
 549         } else {
 550                 /* CAPS-LOCK LED */
 551                 mxc_request_iomux(MX51_PIN_EIM_CS0, IOMUX_CONFIG_GPIO);
 552                 gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_CS0), 0);
 553
 554                 /* ALARM-LED LED */
 555                 mxc_request_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_GPIO);
 556                 gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3), 0);
 557         }
 558 }
 559
 560 void efikamx_toggle_led(uint32_t mask)
 561 {
 562         if (machine_is_efikamx()) {
 563                 gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9),
 564                                 mask & EFIKAMX_LED_BLUE);
 565                 gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC),
 566                                 mask & EFIKAMX_LED_GREEN);
 567                 gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC),
 568                                 mask & EFIKAMX_LED_RED);
 569         } else {
 570                 gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS0),
 571                                 mask & EFIKAMX_LED_BLUE);
 572                 gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3),
 573                                 !(mask & EFIKAMX_LED_GREEN));
 574         }
 575 }
 576
 577 /*
 578  * Board initialization
 579  */
 580 static void init_drive_strength(void)
 581 {
 582         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS);
 583         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE);
 584         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER);
 585         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU);
 586         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST);
 587         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH);
 588         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH);
 589         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS,
 590                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 591         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS,
 592                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 593         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE);
 594         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER);
 595         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE);
 596         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE);
 597         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE);
 598         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE);
 599         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST);
 600         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST);
 601         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST);
 602         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST);
 603         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU);
 604         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS);
 605         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM);
 606         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM);
 607         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM);
 608         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM);
 609
 610         /* Setting pad options */
 611         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE,
 612                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 613                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 614         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0,
 615                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 616                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 617         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1,
 618                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 619                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 620         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK,
 621                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 622                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 623         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0,
 624                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 625                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 626         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1,
 627                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 628                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 629         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2,
 630                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 631                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 632         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3,
 633                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 634                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 635         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0,
 636                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 637                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 638         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1,
 639                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 640                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 641         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0,
 642                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 643                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 644         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1,
 645                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 646                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 647         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2,
 648                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 649                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 650         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3,
 651                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 652                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 653 }
 654
 655 int board_early_init_f(void)
 656 {
 657         init_drive_strength();
 658
 659         setup_iomux_uart();
 660         setup_iomux_spi();
 661         setup_iomux_led();
 662
 663         return 0;
 664 }
 665
 666 int board_init(void)
 667 {
 668         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 669
 670         return 0;
 671 }
 672
 673 int board_late_init(void)
 674 {
 675         setup_iomux_spi();
 676
 677         power_init();
 678
 679         setup_iomux_led();
 680         setup_iomux_ata();
 681
 682         efikamx_toggle_led(EFIKAMX_LED_BLUE);
 683
 684         return 0;
 685 }
 686
 687 int checkboard(void)
 688 {
 689         u32 rev = get_efika_rev();
 690
 691         if (machine_is_efikamx()) {
 692                 printf("Board: Efika MX, rev1.%i\n", rev & 0xf);
 693                 return 0;
 694         } else {
 695                 switch (rev) {
 696                 case EFIKASB_BOARD_REV_13:
 697                         printf("Board: Efika SB rev1.3\n");
 698                         break;
 699                 case EFIKASB_BOARD_REV_20:
 700                         printf("Board: Efika SB rev2.0\n");
 701                         break;
 702                 default:
 703                         printf("Board: Efika SB, rev Unknown\n");
 704                         break;
 705                 }
 706         }
 707
 708         return 0;
 709 }