board/eets/pdu001/mux.c

   1 /*
   2  * mux.c
   3  *
   4  * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
   5  *
   6  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier: GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <asm/arch/sys_proto.h>
  13 #include <asm/arch/hardware.h>
  14 #include <asm/arch/mux.h>
  15 #include <asm/io.h>
  16 #include <i2c.h>
  17 #include "board.h"
  18
  19 static struct module_pin_mux uart0_pin_mux[] = {
  20         {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},  /* UART0_RXD */
  21         {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},              /* UART0_TXD */
  22         {-1},
  23 };
  24
  25 static struct module_pin_mux uart1_pin_mux[] = {
  26         {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},  /* UART1_RXD */
  27         {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},              /* UART1_TXD */
  28         {-1},
  29 };
  30
  31 static struct module_pin_mux uart2_pin_mux[] = {
  32         {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)},  /* UART2_RXD */
  33         {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)},                /* UART2_TXD */
  34         {-1},
  35 };
  36
  37 static struct module_pin_mux uart3_pin_mux[] = {
  38         {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)},   /* UART3_RXD */
  39         {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)},      /* UART3_TXD */
  40         {-1},
  41 };
  42
  43 static struct module_pin_mux uart4_pin_mux[] = {
  44         {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
  45         {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)},               /* UART4_TXD */
  46         {-1},
  47 };
  48
  49 static struct module_pin_mux uart5_pin_mux[] = {
  50         {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)},  /* UART5_RXD */
  51         {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)},              /* UART5_TXD */
  52         {-1},
  53 };
  54
  55 static struct module_pin_mux i2c0_pin_mux[] = {
  56         {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
  57                         PULLUDEN | SLEWCTRL)},                  /* I2C_DATA  */
  58         {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
  59                         PULLUDEN | SLEWCTRL)},                  /* I2C_SCLK  */
  60         {-1},
  61 };
  62
  63 void enable_uart0_pin_mux(void)
  64 {
  65         configure_module_pin_mux(uart0_pin_mux);
  66 }
  67
  68 void enable_uart1_pin_mux(void)
  69 {
  70         configure_module_pin_mux(uart1_pin_mux);
  71 }
  72
  73 void enable_uart2_pin_mux(void)
  74 {
  75         configure_module_pin_mux(uart2_pin_mux);
  76 }
  77
  78 void enable_uart3_pin_mux(void)
  79 {
  80         configure_module_pin_mux(uart3_pin_mux);
  81 }
  82
  83 void enable_uart4_pin_mux(void)
  84 {
  85         configure_module_pin_mux(uart4_pin_mux);
  86 }
  87
  88 void enable_uart5_pin_mux(void)
  89 {
  90         configure_module_pin_mux(uart5_pin_mux);
  91 }
  92
  93 void enable_uart_pin_mux(u32 addr)
  94 {
  95         switch (addr) {
  96         case CONFIG_SYS_NS16550_COM1:
  97                 enable_uart0_pin_mux();
  98                 break;
  99         case CONFIG_SYS_NS16550_COM2:
 100                 enable_uart1_pin_mux();
 101                 break;
 102         case CONFIG_SYS_NS16550_COM3:
 103                 enable_uart2_pin_mux();
 104                 break;
 105         case CONFIG_SYS_NS16550_COM4:
 106                 enable_uart3_pin_mux();
 107                 break;
 108         case CONFIG_SYS_NS16550_COM5:
 109                 enable_uart4_pin_mux();
 110                 break;
 111         case CONFIG_SYS_NS16550_COM6:
 112                 enable_uart5_pin_mux();
 113                 break;
 114         }
 115 }
 116
 117 void enable_i2c0_pin_mux(void)
 118 {
 119         configure_module_pin_mux(i2c0_pin_mux);
 120 }