2 * PLL register values for Cirrus edb93xx boards
4 * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/ep93xx.h>
28 #if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \
29 defined(CONFIG_EDB9302A)
31 * fclk_div: 2, nbyp1: 1, hclk_div: 5, pclk_div: 2
32 * pll1_x1: 294912000.000000, pll1_x2ip: 36864000.000000,
33 * pll1_x2: 331776000.000000, pll1_out: 331776000.000000
35 #define CLKSET1_VAL (7 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
36 8 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
37 19 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
38 1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \
39 3 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \
40 SYSCON_CLKSET1_NBYP1 | \
41 1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT)
42 #elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) || \
43 defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) || \
44 defined(CONFIG_EDB9315A)
46 * fclk_div: 2, nbyp1: 1, hclk_div: 4, pclk_div: 2
47 * pll1_x1: 3096576000.000000, pll1_x2ip: 129024000.000000,
48 * pll1_x2: 3999744000.000000, pll1_out: 1999872000.000000
50 #define CLKSET1_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
51 30 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
52 20 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
53 1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \
54 2 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \
55 SYSCON_CLKSET1_NBYP1 | \
56 1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT)
58 #error "Undefined board"
62 * usb_div: 4, nbyp2: 1, pll2_en: 1
63 * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000,
64 * pll2_x2: 384000000.000000, pll2_out: 192000000.000000
66 #define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
67 24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
68 24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
69 1 << SYSCON_CLKSET_PLL_PS_SHIFT | \
70 SYSCON_CLKSET2_PLL2_EN | \
71 SYSCON_CLKSET2_NBYP2 | \
72 3 << SYSCON_CLKSET2_USB_DIV_SHIFT)