2 * PLL setup for Cirrus edb93xx boards
4 * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
6 * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include "early_udelay.h"
34 struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
37 writel(CLKSET1_VAL, &syscon->clkset1);
41 * writing to CLKSET1 causes the EP93xx to enter standby for between
42 * 8 ms to 16 ms, until PLL1 stabilizes
51 writel(CLKSET2_VAL, &syscon->clkset2);
54 * the user's guide recommends to wait at least 1 ms for PLL2 to