1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
8 #include <asm/arch/stm32.h>
9 #include <asm/arch/sys_proto.h>
16 #include <dm/device.h>
17 #include <dm/uclass.h>
19 #include <env_internal.h>
21 #include <generic-phy.h>
24 #include <i2c_eeprom.h>
33 #include <power/regulator.h>
34 #include <remoteproc.h>
38 #include <usb/dwc2_udc.h>
41 /* SYSCFG registers */
42 #define SYSCFG_BOOTR 0x00
43 #define SYSCFG_PMCSETR 0x04
44 #define SYSCFG_IOCTRLSETR 0x18
45 #define SYSCFG_ICNR 0x1C
46 #define SYSCFG_CMPCR 0x20
47 #define SYSCFG_CMPENSETR 0x24
48 #define SYSCFG_PMCCLRR 0x44
50 #define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0)
51 #define SYSCFG_BOOTR_BOOTPD_SHIFT 4
53 #define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0)
54 #define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1)
55 #define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2)
56 #define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3)
57 #define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4)
59 #define SYSCFG_CMPCR_SW_CTRL BIT(1)
60 #define SYSCFG_CMPCR_READY BIT(8)
62 #define SYSCFG_CMPENSETR_MPU_EN BIT(0)
64 #define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16)
65 #define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17)
67 #define SYSCFG_PMCSETR_ETH_SELMII BIT(20)
69 #define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21)
70 #define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0
71 #define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21)
72 #define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23)
75 * Get a global data pointer
77 DECLARE_GLOBAL_DATA_PTR;
79 int setup_mac_address(void)
81 unsigned char enetaddr[6];
85 ret = eth_env_get_enetaddr("ethaddr", enetaddr);
86 if (ret) /* ethaddr is already set */
89 off = fdt_path_offset(gd->fdt_blob, "eeprom0");
91 printf("%s: No eeprom0 path offset\n", __func__);
95 ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
97 printf("Cannot find EEPROM!\n");
101 ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
103 printf("Error reading configuration EEPROM!\n");
107 if (is_valid_ethaddr(enetaddr))
108 eth_env_set_enetaddr("ethaddr", enetaddr);
116 const char *fdt_compat;
119 if (IS_ENABLED(CONFIG_TFABOOT))
124 printf("Board: stm32mp1 in %s mode", mode);
125 fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
127 if (fdt_compat && fdt_compat_len)
128 printf(" (%s)", fdt_compat);
134 #ifdef CONFIG_BOARD_EARLY_INIT_F
135 static u8 brdcode __section("data");
136 static u8 ddr3code __section("data");
137 static u8 somcode __section("data");
139 static void board_get_coding_straps(void)
141 struct gpio_desc gpio[4];
145 node = ofnode_path("/config");
146 if (!ofnode_valid(node)) {
147 printf("%s: no /config node?\n", __func__);
155 ret = gpio_request_list_by_name_nodev(node, "dh,som-coding-gpios",
156 gpio, ARRAY_SIZE(gpio),
158 for (i = 0; i < ret; i++)
159 somcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
161 ret = gpio_request_list_by_name_nodev(node, "dh,ddr3-coding-gpios",
162 gpio, ARRAY_SIZE(gpio),
164 for (i = 0; i < ret; i++)
165 ddr3code |= !!dm_gpio_get_value(&(gpio[i])) << i;
167 ret = gpio_request_list_by_name_nodev(node, "dh,board-coding-gpios",
168 gpio, ARRAY_SIZE(gpio),
170 for (i = 0; i < ret; i++)
171 brdcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
173 printf("Code: SoM:rev=%d,ddr3=%d Board:rev=%d\n",
174 somcode, ddr3code, brdcode);
177 int board_stm32mp1_ddr_config_name_match(struct udevice *dev,
181 !strcmp(name, "st,ddr3-1066-888-bin-g-1x4gb-533mhz"))
185 !strcmp(name, "st,ddr3-1066-888-bin-g-2x4gb-533mhz"))
191 int board_early_init_f(void)
193 board_get_coding_straps();
198 #ifdef CONFIG_SPL_LOAD_FIT
199 int board_fit_config_name_match(const char *name)
203 snprintf(test, sizeof(test), "somrev%d_boardrev%d", somcode, brdcode);
205 if (!strcmp(name, test))
213 static void board_key_check(void)
215 #if defined(CONFIG_FASTBOOT) || defined(CONFIG_CMD_STM32PROG)
217 struct gpio_desc gpio;
218 enum forced_boot_mode boot_mode = BOOT_NORMAL;
220 node = ofnode_path("/config");
221 if (!ofnode_valid(node)) {
222 debug("%s: no /config node?\n", __func__);
225 #ifdef CONFIG_FASTBOOT
226 if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0,
227 &gpio, GPIOD_IS_IN)) {
228 debug("%s: could not find a /config/st,fastboot-gpios\n",
231 if (dm_gpio_get_value(&gpio)) {
232 puts("Fastboot key pressed, ");
233 boot_mode = BOOT_FASTBOOT;
236 dm_gpio_free(NULL, &gpio);
239 #ifdef CONFIG_CMD_STM32PROG
240 if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0,
241 &gpio, GPIOD_IS_IN)) {
242 debug("%s: could not find a /config/st,stm32prog-gpios\n",
245 if (dm_gpio_get_value(&gpio)) {
246 puts("STM32Programmer key pressed, ");
247 boot_mode = BOOT_STM32PROG;
249 dm_gpio_free(NULL, &gpio);
253 if (boot_mode != BOOT_NORMAL) {
254 puts("entering download mode...\n");
255 clrsetbits_le32(TAMP_BOOT_CONTEXT,
256 TAMP_BOOT_FORCED_MASK,
262 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
264 #include <usb/dwc2_udc.h>
265 int g_dnl_board_usb_cable_connected(void)
267 struct udevice *dwc2_udc_otg;
270 ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC,
271 DM_GET_DRIVER(dwc2_udc_otg),
274 debug("dwc2_udc_otg init failed\n");
276 return dwc2_udc_B_session_valid(dwc2_udc_otg);
279 #define STM32MP1_G_DNL_DFU_PRODUCT_NUM 0xdf11
280 #define STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM 0x0afb
282 int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
284 if (!strcmp(name, "usb_dnl_dfu"))
285 put_unaligned(STM32MP1_G_DNL_DFU_PRODUCT_NUM, &dev->idProduct);
286 else if (!strcmp(name, "usb_dnl_fastboot"))
287 put_unaligned(STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM,
290 put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct);
295 #endif /* CONFIG_USB_GADGET */
298 static int get_led(struct udevice **dev, char *led_string)
303 led_name = fdtdec_get_config_string(gd->fdt_blob, led_string);
305 pr_debug("%s: could not find %s config string\n",
306 __func__, led_string);
309 ret = led_get_by_label(led_name, dev);
311 debug("%s: get=%d\n", __func__, ret);
318 static int setup_led(enum led_state_t cmd)
323 ret = get_led(&dev, "u-boot,boot-led");
327 ret = led_set_state(dev, cmd);
332 static void __maybe_unused led_error_blink(u32 nb_blink)
344 ret = get_led(&led, "u-boot,error-led");
346 /* make u-boot,error-led blinking */
347 /* if U32_MAX and 125ms interval, for 17.02 years */
348 for (i = 0; i < 2 * nb_blink; i++) {
349 led_set_state(led, LEDST_TOGGLE);
356 /* infinite: the boot process must be stopped */
357 if (nb_blink == U32_MAX)
361 static void sysconf_init(void)
363 #ifndef CONFIG_TFABOOT
365 #ifdef CONFIG_DM_REGULATOR
366 struct udevice *pwr_dev;
367 struct udevice *pwr_reg;
374 syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
376 /* interconnect update : select master using the port 1 */
379 /* today information is hardcoded in U-Boot */
380 writel(BIT(9), syscfg + SYSCFG_ICNR);
382 /* disable Pull-Down for boot pin connected to VDD */
383 bootr = readl(syscfg + SYSCFG_BOOTR);
384 bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT);
385 bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT;
386 writel(bootr, syscfg + SYSCFG_BOOTR);
388 #ifdef CONFIG_DM_REGULATOR
389 /* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
390 * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection.
391 * The customer will have to disable this for low frequencies
392 * or if AFMUX is selected but the function not used, typically for
393 * TRACE. Otherwise, impact on power consumption.
396 * enabling High Speed mode while VDD>2.7V
397 * with the OTP product_below_2v5 (OTP 18, BIT 13)
398 * erroneously set to 1 can damage the IC!
399 * => U-Boot set the register only if VDD < 2.7V (in DT)
400 * but this value need to be consistent with board design
402 ret = uclass_get_device_by_driver(UCLASS_PMIC,
403 DM_GET_DRIVER(stm32mp_pwr_pmic),
406 ret = uclass_get_device_by_driver(UCLASS_MISC,
407 DM_GET_DRIVER(stm32mp_bsec),
410 pr_err("Can't find stm32mp_bsec driver\n");
414 ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4);
418 /* get VDD = vdd-supply */
419 ret = device_get_supply_regulator(pwr_dev, "vdd-supply",
422 /* check if VDD is Low Voltage */
424 if (regulator_get_value(pwr_reg) < 2700000) {
425 writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
426 SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
427 SYSCFG_IOCTRLSETR_HSLVEN_ETH |
428 SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
429 SYSCFG_IOCTRLSETR_HSLVEN_SPI,
430 syscfg + SYSCFG_IOCTRLSETR);
433 pr_err("product_below_2v5=0: HSLVEN protected by HW\n");
436 pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n");
439 debug("VDD unknown");
444 /* activate automatic I/O compensation
445 * warning: need to ensure CSI enabled and ready in clock driver
447 writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR);
449 while (!(readl(syscfg + SYSCFG_CMPCR) & SYSCFG_CMPCR_READY))
451 clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
455 static void board_init_fmc2(void)
457 #define STM32_FMC2_BCR1 0x0
458 #define STM32_FMC2_BTR1 0x4
459 #define STM32_FMC2_BWTR1 0x104
460 #define STM32_FMC2_BCR(x) ((x) * 0x8 + STM32_FMC2_BCR1)
461 #define STM32_FMC2_BCRx_FMCEN BIT(31)
462 #define STM32_FMC2_BCRx_WREN BIT(12)
463 #define STM32_FMC2_BCRx_RSVD BIT(7)
464 #define STM32_FMC2_BCRx_FACCEN BIT(6)
465 #define STM32_FMC2_BCRx_MWID(n) ((n) << 4)
466 #define STM32_FMC2_BCRx_MTYP(n) ((n) << 2)
467 #define STM32_FMC2_BCRx_MUXEN BIT(1)
468 #define STM32_FMC2_BCRx_MBKEN BIT(0)
469 #define STM32_FMC2_BTR(x) ((x) * 0x8 + STM32_FMC2_BTR1)
470 #define STM32_FMC2_BTRx_DATAHLD(n) ((n) << 30)
471 #define STM32_FMC2_BTRx_BUSTURN(n) ((n) << 16)
472 #define STM32_FMC2_BTRx_DATAST(n) ((n) << 8)
473 #define STM32_FMC2_BTRx_ADDHLD(n) ((n) << 4)
474 #define STM32_FMC2_BTRx_ADDSET(n) ((n) << 0)
476 #define RCC_MP_AHB6RSTCLRR 0x218
477 #define RCC_MP_AHB6RSTCLRR_FMCRST BIT(12)
478 #define RCC_MP_AHB6ENSETR 0x19c
479 #define RCC_MP_AHB6ENSETR_FMCEN BIT(12)
481 const u32 bcr = STM32_FMC2_BCRx_WREN |STM32_FMC2_BCRx_RSVD |
482 STM32_FMC2_BCRx_FACCEN | STM32_FMC2_BCRx_MWID(1) |
483 STM32_FMC2_BCRx_MTYP(2) | STM32_FMC2_BCRx_MUXEN |
484 STM32_FMC2_BCRx_MBKEN;
485 const u32 btr = STM32_FMC2_BTRx_DATAHLD(3) |
486 STM32_FMC2_BTRx_BUSTURN(2) |
487 STM32_FMC2_BTRx_DATAST(0x22) |
488 STM32_FMC2_BTRx_ADDHLD(2) |
489 STM32_FMC2_BTRx_ADDSET(2);
491 /* Set up FMC2 bus for KS8851-16MLL and X11 SRAM */
492 writel(RCC_MP_AHB6RSTCLRR_FMCRST, STM32_RCC_BASE + RCC_MP_AHB6RSTCLRR);
493 writel(RCC_MP_AHB6ENSETR_FMCEN, STM32_RCC_BASE + RCC_MP_AHB6ENSETR);
495 /* KS8851-16MLL -- Muxed mode */
496 writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(1));
497 writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(1));
498 /* AS7C34098 SRAM on X11 -- Muxed mode */
499 writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(3));
500 writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(3));
502 setbits_le32(STM32_FMC2_BASE + STM32_FMC2_BCR1, STM32_FMC2_BCRx_FMCEN);
505 /* board dependent setup after realloc */
510 /* address of boot parameters */
511 gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
513 /* probe all PINCTRL for hog */
514 for (uclass_first_device(UCLASS_PINCTRL, &dev);
516 uclass_next_device(&dev)) {
517 pr_debug("probe pincontrol = %s\n", dev->name);
522 #ifdef CONFIG_DM_REGULATOR
523 regulators_enable_boot_on(_DEBUG);
530 if (CONFIG_IS_ENABLED(LED))
536 int board_late_init(void)
539 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
540 const void *fdt_compat;
543 fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
545 if (fdt_compat && fdt_compat_len) {
546 if (strncmp(fdt_compat, "st,", 3) != 0)
547 env_set("board_name", fdt_compat);
549 env_set("board_name", fdt_compat + 3);
553 /* Check the boot-source to disable bootdelay */
554 boot_device = env_get("boot_device");
555 if (!strcmp(boot_device, "serial") || !strcmp(boot_device, "usb"))
556 env_set("bootdelay", "0");
558 #ifdef CONFIG_BOARD_EARLY_INIT_F
559 env_set_ulong("dh_som_rev", somcode);
560 env_set_ulong("dh_board_rev", brdcode);
561 env_set_ulong("dh_ddr3_code", ddr3code);
567 void board_quiesce_devices(void)
570 setup_led(LEDST_OFF);
574 /* eth init function : weak called in eqos driver */
575 int board_interface_eth_init(struct udevice *dev,
576 phy_interface_t interface_type)
580 bool eth_clk_sel_reg = false;
581 bool eth_ref_clk_sel_reg = false;
583 /* Gigabit Ethernet 125MHz clock selection. */
584 eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
586 /* Ethernet 50Mhz RMII clock selection */
587 eth_ref_clk_sel_reg =
588 dev_read_bool(dev, "st,eth_ref_clk_sel");
590 syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
595 switch (interface_type) {
596 case PHY_INTERFACE_MODE_MII:
597 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
598 SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
599 debug("%s: PHY_INTERFACE_MODE_MII\n", __func__);
601 case PHY_INTERFACE_MODE_GMII:
603 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
604 SYSCFG_PMCSETR_ETH_CLK_SEL;
606 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
607 debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__);
609 case PHY_INTERFACE_MODE_RMII:
610 if (eth_ref_clk_sel_reg)
611 value = SYSCFG_PMCSETR_ETH_SEL_RMII |
612 SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
614 value = SYSCFG_PMCSETR_ETH_SEL_RMII;
615 debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__);
617 case PHY_INTERFACE_MODE_RGMII:
618 case PHY_INTERFACE_MODE_RGMII_ID:
619 case PHY_INTERFACE_MODE_RGMII_RXID:
620 case PHY_INTERFACE_MODE_RGMII_TXID:
622 value = SYSCFG_PMCSETR_ETH_SEL_RGMII |
623 SYSCFG_PMCSETR_ETH_CLK_SEL;
625 value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
626 debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__);
629 debug("%s: Do not manage %d interface\n",
630 __func__, interface_type);
631 /* Do not manage others interfaces */
635 /* clear and set ETH configuration bits */
636 writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII |
637 SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL,
638 syscfg + SYSCFG_PMCCLRR);
639 writel(value, syscfg + SYSCFG_PMCSETR);
644 enum env_location env_get_location(enum env_operation op, int prio)
649 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
650 return ENVL_SPI_FLASH;
656 #if defined(CONFIG_OF_BOARD_SETUP)
657 int ft_board_setup(void *blob, bd_t *bd)
663 static void board_copro_image_process(ulong fw_image, size_t fw_size)
665 int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */
667 if (!rproc_is_initialized())
669 printf("Remote Processor %d initialization failed\n",
674 ret = rproc_load(id, fw_image, fw_size);
675 printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
676 id, fw_image, fw_size, ret ? " Failed!" : " Success!");
680 env_set("copro_state", "booted");
684 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process);