1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
8 #include <asm/arch/stm32.h>
9 #include <asm/arch/sys_proto.h>
16 #include <dm/device.h>
17 #include <dm/uclass.h>
19 #include <env_internal.h>
21 #include <generic-phy.h>
24 #include <i2c_eeprom.h>
33 #include <power/regulator.h>
34 #include <remoteproc.h>
38 #include <usb/dwc2_udc.h>
41 /* SYSCFG registers */
42 #define SYSCFG_BOOTR 0x00
43 #define SYSCFG_PMCSETR 0x04
44 #define SYSCFG_IOCTRLSETR 0x18
45 #define SYSCFG_ICNR 0x1C
46 #define SYSCFG_CMPCR 0x20
47 #define SYSCFG_CMPENSETR 0x24
48 #define SYSCFG_PMCCLRR 0x44
50 #define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0)
51 #define SYSCFG_BOOTR_BOOTPD_SHIFT 4
53 #define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0)
54 #define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1)
55 #define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2)
56 #define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3)
57 #define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4)
59 #define SYSCFG_CMPCR_SW_CTRL BIT(1)
60 #define SYSCFG_CMPCR_READY BIT(8)
62 #define SYSCFG_CMPENSETR_MPU_EN BIT(0)
64 #define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16)
65 #define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17)
67 #define SYSCFG_PMCSETR_ETH_SELMII BIT(20)
69 #define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21)
70 #define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0
71 #define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21)
72 #define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23)
75 * Get a global data pointer
77 DECLARE_GLOBAL_DATA_PTR;
79 int setup_mac_address(void)
81 unsigned char enetaddr[6];
85 ret = eth_env_get_enetaddr("ethaddr", enetaddr);
86 if (ret) /* ethaddr is already set */
89 off = fdt_path_offset(gd->fdt_blob, "eeprom0");
91 printf("%s: No eeprom0 path offset\n", __func__);
95 ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
97 printf("Cannot find EEPROM!\n");
101 ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
103 printf("Error reading configuration EEPROM!\n");
107 if (is_valid_ethaddr(enetaddr))
108 eth_env_set_enetaddr("ethaddr", enetaddr);
116 const char *fdt_compat;
119 if (IS_ENABLED(CONFIG_STM32MP1_OPTEE))
120 mode = "trusted with OP-TEE";
121 else if (IS_ENABLED(CONFIG_TFABOOT))
126 printf("Board: stm32mp1 in %s mode", mode);
127 fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
129 if (fdt_compat && fdt_compat_len)
130 printf(" (%s)", fdt_compat);
136 static void board_key_check(void)
138 #if defined(CONFIG_FASTBOOT) || defined(CONFIG_CMD_STM32PROG)
140 struct gpio_desc gpio;
141 enum forced_boot_mode boot_mode = BOOT_NORMAL;
143 node = ofnode_path("/config");
144 if (!ofnode_valid(node)) {
145 debug("%s: no /config node?\n", __func__);
148 #ifdef CONFIG_FASTBOOT
149 if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0,
150 &gpio, GPIOD_IS_IN)) {
151 debug("%s: could not find a /config/st,fastboot-gpios\n",
154 if (dm_gpio_get_value(&gpio)) {
155 puts("Fastboot key pressed, ");
156 boot_mode = BOOT_FASTBOOT;
159 dm_gpio_free(NULL, &gpio);
162 #ifdef CONFIG_CMD_STM32PROG
163 if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0,
164 &gpio, GPIOD_IS_IN)) {
165 debug("%s: could not find a /config/st,stm32prog-gpios\n",
168 if (dm_gpio_get_value(&gpio)) {
169 puts("STM32Programmer key pressed, ");
170 boot_mode = BOOT_STM32PROG;
172 dm_gpio_free(NULL, &gpio);
176 if (boot_mode != BOOT_NORMAL) {
177 puts("entering download mode...\n");
178 clrsetbits_le32(TAMP_BOOT_CONTEXT,
179 TAMP_BOOT_FORCED_MASK,
185 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
187 #include <usb/dwc2_udc.h>
188 int g_dnl_board_usb_cable_connected(void)
190 struct udevice *dwc2_udc_otg;
193 ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC,
194 DM_GET_DRIVER(dwc2_udc_otg),
197 debug("dwc2_udc_otg init failed\n");
199 return dwc2_udc_B_session_valid(dwc2_udc_otg);
202 #define STM32MP1_G_DNL_DFU_PRODUCT_NUM 0xdf11
203 #define STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM 0x0afb
205 int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
207 if (!strcmp(name, "usb_dnl_dfu"))
208 put_unaligned(STM32MP1_G_DNL_DFU_PRODUCT_NUM, &dev->idProduct);
209 else if (!strcmp(name, "usb_dnl_fastboot"))
210 put_unaligned(STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM,
213 put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct);
218 #endif /* CONFIG_USB_GADGET */
221 static int get_led(struct udevice **dev, char *led_string)
226 led_name = fdtdec_get_config_string(gd->fdt_blob, led_string);
228 pr_debug("%s: could not find %s config string\n",
229 __func__, led_string);
232 ret = led_get_by_label(led_name, dev);
234 debug("%s: get=%d\n", __func__, ret);
241 static int setup_led(enum led_state_t cmd)
246 ret = get_led(&dev, "u-boot,boot-led");
250 ret = led_set_state(dev, cmd);
255 static void __maybe_unused led_error_blink(u32 nb_blink)
267 ret = get_led(&led, "u-boot,error-led");
269 /* make u-boot,error-led blinking */
270 /* if U32_MAX and 125ms interval, for 17.02 years */
271 for (i = 0; i < 2 * nb_blink; i++) {
272 led_set_state(led, LEDST_TOGGLE);
279 /* infinite: the boot process must be stopped */
280 if (nb_blink == U32_MAX)
284 static void sysconf_init(void)
286 #ifndef CONFIG_TFABOOT
288 #ifdef CONFIG_DM_REGULATOR
289 struct udevice *pwr_dev;
290 struct udevice *pwr_reg;
297 syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
299 /* interconnect update : select master using the port 1 */
302 /* today information is hardcoded in U-Boot */
303 writel(BIT(9), syscfg + SYSCFG_ICNR);
305 /* disable Pull-Down for boot pin connected to VDD */
306 bootr = readl(syscfg + SYSCFG_BOOTR);
307 bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT);
308 bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT;
309 writel(bootr, syscfg + SYSCFG_BOOTR);
311 #ifdef CONFIG_DM_REGULATOR
312 /* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
313 * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection.
314 * The customer will have to disable this for low frequencies
315 * or if AFMUX is selected but the function not used, typically for
316 * TRACE. Otherwise, impact on power consumption.
319 * enabling High Speed mode while VDD>2.7V
320 * with the OTP product_below_2v5 (OTP 18, BIT 13)
321 * erroneously set to 1 can damage the IC!
322 * => U-Boot set the register only if VDD < 2.7V (in DT)
323 * but this value need to be consistent with board design
325 ret = uclass_get_device_by_driver(UCLASS_PMIC,
326 DM_GET_DRIVER(stm32mp_pwr_pmic),
329 ret = uclass_get_device_by_driver(UCLASS_MISC,
330 DM_GET_DRIVER(stm32mp_bsec),
333 pr_err("Can't find stm32mp_bsec driver\n");
337 ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4);
341 /* get VDD = vdd-supply */
342 ret = device_get_supply_regulator(pwr_dev, "vdd-supply",
345 /* check if VDD is Low Voltage */
347 if (regulator_get_value(pwr_reg) < 2700000) {
348 writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
349 SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
350 SYSCFG_IOCTRLSETR_HSLVEN_ETH |
351 SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
352 SYSCFG_IOCTRLSETR_HSLVEN_SPI,
353 syscfg + SYSCFG_IOCTRLSETR);
356 pr_err("product_below_2v5=0: HSLVEN protected by HW\n");
359 pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n");
362 debug("VDD unknown");
367 /* activate automatic I/O compensation
368 * warning: need to ensure CSI enabled and ready in clock driver
370 writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR);
372 while (!(readl(syscfg + SYSCFG_CMPCR) & SYSCFG_CMPCR_READY))
374 clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
378 static void board_init_fmc2(void)
380 #define STM32_FMC2_BCR1 0x0
381 #define STM32_FMC2_BTR1 0x4
382 #define STM32_FMC2_BWTR1 0x104
383 #define STM32_FMC2_BCR(x) ((x) * 0x8 + STM32_FMC2_BCR1)
384 #define STM32_FMC2_BCRx_FMCEN BIT(31)
385 #define STM32_FMC2_BCRx_WREN BIT(12)
386 #define STM32_FMC2_BCRx_RSVD BIT(7)
387 #define STM32_FMC2_BCRx_FACCEN BIT(6)
388 #define STM32_FMC2_BCRx_MWID(n) ((n) << 4)
389 #define STM32_FMC2_BCRx_MTYP(n) ((n) << 2)
390 #define STM32_FMC2_BCRx_MUXEN BIT(1)
391 #define STM32_FMC2_BCRx_MBKEN BIT(0)
392 #define STM32_FMC2_BTR(x) ((x) * 0x8 + STM32_FMC2_BTR1)
393 #define STM32_FMC2_BTRx_DATAHLD(n) ((n) << 30)
394 #define STM32_FMC2_BTRx_BUSTURN(n) ((n) << 16)
395 #define STM32_FMC2_BTRx_DATAST(n) ((n) << 8)
396 #define STM32_FMC2_BTRx_ADDHLD(n) ((n) << 4)
397 #define STM32_FMC2_BTRx_ADDSET(n) ((n) << 0)
399 #define RCC_MP_AHB6RSTCLRR 0x218
400 #define RCC_MP_AHB6RSTCLRR_FMCRST BIT(12)
401 #define RCC_MP_AHB6ENSETR 0x19c
402 #define RCC_MP_AHB6ENSETR_FMCEN BIT(12)
404 const u32 bcr = STM32_FMC2_BCRx_WREN |STM32_FMC2_BCRx_RSVD |
405 STM32_FMC2_BCRx_FACCEN | STM32_FMC2_BCRx_MWID(1) |
406 STM32_FMC2_BCRx_MTYP(2) | STM32_FMC2_BCRx_MUXEN |
407 STM32_FMC2_BCRx_MBKEN;
408 const u32 btr = STM32_FMC2_BTRx_DATAHLD(3) |
409 STM32_FMC2_BTRx_BUSTURN(2) |
410 STM32_FMC2_BTRx_DATAST(0x22) |
411 STM32_FMC2_BTRx_ADDHLD(2) |
412 STM32_FMC2_BTRx_ADDSET(2);
414 /* Set up FMC2 bus for KS8851-16MLL and X11 SRAM */
415 writel(RCC_MP_AHB6RSTCLRR_FMCRST, STM32_RCC_BASE + RCC_MP_AHB6RSTCLRR);
416 writel(RCC_MP_AHB6ENSETR_FMCEN, STM32_RCC_BASE + RCC_MP_AHB6ENSETR);
418 /* KS8851-16MLL -- Muxed mode */
419 writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(1));
420 writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(1));
421 /* AS7C34098 SRAM on X11 -- Muxed mode */
422 writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(3));
423 writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(3));
425 setbits_le32(STM32_FMC2_BASE + STM32_FMC2_BCR1, STM32_FMC2_BCRx_FMCEN);
428 /* board dependent setup after realloc */
433 /* address of boot parameters */
434 gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
436 /* probe all PINCTRL for hog */
437 for (uclass_first_device(UCLASS_PINCTRL, &dev);
439 uclass_next_device(&dev)) {
440 pr_debug("probe pincontrol = %s\n", dev->name);
445 #ifdef CONFIG_DM_REGULATOR
446 regulators_enable_boot_on(_DEBUG);
453 if (CONFIG_IS_ENABLED(LED))
459 int board_late_init(void)
462 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
463 const void *fdt_compat;
466 fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
468 if (fdt_compat && fdt_compat_len) {
469 if (strncmp(fdt_compat, "st,", 3) != 0)
470 env_set("board_name", fdt_compat);
472 env_set("board_name", fdt_compat + 3);
476 /* Check the boot-source to disable bootdelay */
477 boot_device = env_get("boot_device");
478 if (!strcmp(boot_device, "serial") || !strcmp(boot_device, "usb"))
479 env_set("bootdelay", "0");
484 void board_quiesce_devices(void)
487 setup_led(LEDST_OFF);
491 /* eth init function : weak called in eqos driver */
492 int board_interface_eth_init(struct udevice *dev,
493 phy_interface_t interface_type)
497 bool eth_clk_sel_reg = false;
498 bool eth_ref_clk_sel_reg = false;
500 /* Gigabit Ethernet 125MHz clock selection. */
501 eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
503 /* Ethernet 50Mhz RMII clock selection */
504 eth_ref_clk_sel_reg =
505 dev_read_bool(dev, "st,eth_ref_clk_sel");
507 syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
512 switch (interface_type) {
513 case PHY_INTERFACE_MODE_MII:
514 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
515 SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
516 debug("%s: PHY_INTERFACE_MODE_MII\n", __func__);
518 case PHY_INTERFACE_MODE_GMII:
520 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
521 SYSCFG_PMCSETR_ETH_CLK_SEL;
523 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
524 debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__);
526 case PHY_INTERFACE_MODE_RMII:
527 if (eth_ref_clk_sel_reg)
528 value = SYSCFG_PMCSETR_ETH_SEL_RMII |
529 SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
531 value = SYSCFG_PMCSETR_ETH_SEL_RMII;
532 debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__);
534 case PHY_INTERFACE_MODE_RGMII:
535 case PHY_INTERFACE_MODE_RGMII_ID:
536 case PHY_INTERFACE_MODE_RGMII_RXID:
537 case PHY_INTERFACE_MODE_RGMII_TXID:
539 value = SYSCFG_PMCSETR_ETH_SEL_RGMII |
540 SYSCFG_PMCSETR_ETH_CLK_SEL;
542 value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
543 debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__);
546 debug("%s: Do not manage %d interface\n",
547 __func__, interface_type);
548 /* Do not manage others interfaces */
552 /* clear and set ETH configuration bits */
553 writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII |
554 SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL,
555 syscfg + SYSCFG_PMCCLRR);
556 writel(value, syscfg + SYSCFG_PMCSETR);
561 enum env_location env_get_location(enum env_operation op, int prio)
566 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
567 return ENVL_SPI_FLASH;
573 #ifdef CONFIG_SYS_MTDPARTS_RUNTIME
575 #define MTDPARTS_LEN 256
576 #define MTDIDS_LEN 128
579 * The mtdparts_nand0 and mtdparts_nor0 variable tends to be long.
580 * If we need to access it before the env is relocated, then we need
581 * to use our own stack buffer. gd->env_buf will be too small.
583 * @param buf temporary buffer pointer MTDPARTS_LEN long
584 * @return mtdparts variable string, NULL if not found
586 static const char *env_get_mtdparts(const char *str, char *buf)
588 if (gd->flags & GD_FLG_ENV_READY)
590 if (env_get_f(str, buf, MTDPARTS_LEN) != -1)
597 * update the variables "mtdids" and "mtdparts" with content of mtdparts_<dev>
599 static void board_get_mtdparts(const char *dev,
603 char env_name[32] = "mtdparts_";
604 char tmp_mtdparts[MTDPARTS_LEN];
607 /* name of env variable to read = mtdparts_<dev> */
608 strcat(env_name, dev);
609 tmp = env_get_mtdparts(env_name, tmp_mtdparts);
611 /* mtdids: "<dev>=<dev>, ...." */
612 if (mtdids[0] != '\0')
618 /* mtdparts: "mtdparts=<dev>:<mtdparts_<dev>>;..." */
619 if (mtdparts[0] != '\0')
620 strncat(mtdparts, ";", MTDPARTS_LEN);
622 strcat(mtdparts, "mtdparts=");
623 strncat(mtdparts, dev, MTDPARTS_LEN);
624 strncat(mtdparts, ":", MTDPARTS_LEN);
625 strncat(mtdparts, tmp, MTDPARTS_LEN);
629 void board_mtdparts_default(const char **mtdids, const char **mtdparts)
632 static char parts[3 * MTDPARTS_LEN + 1];
633 static char ids[MTDIDS_LEN + 1];
634 static bool mtd_initialized;
636 if (mtd_initialized) {
642 memset(parts, 0, sizeof(parts));
643 memset(ids, 0, sizeof(ids));
645 /* probe all MTD devices */
646 for (uclass_first_device(UCLASS_MTD, &dev);
648 uclass_next_device(&dev)) {
649 pr_debug("mtd device = %s\n", dev->name);
652 if (!uclass_get_device(UCLASS_SPI_FLASH, 0, &dev))
653 board_get_mtdparts("nor0", ids, parts);
655 mtd_initialized = true;
658 debug("%s:mtdids=%s & mtdparts=%s\n", __func__, ids, parts);
662 #if defined(CONFIG_OF_BOARD_SETUP)
663 int ft_board_setup(void *blob, bd_t *bd)
669 #ifdef CONFIG_SET_DFU_ALT_INFO
670 #define DFU_ALT_BUF_LEN SZ_1K
672 static void board_get_alt_info(const char *dev, char *buff)
674 char var_name[32] = "dfu_alt_info_";
677 ALLOC_CACHE_ALIGN_BUFFER(char, tmp_alt, DFU_ALT_BUF_LEN);
679 /* name of env variable to read = dfu_alt_info_<dev> */
680 strcat(var_name, dev);
681 ret = env_get_f(var_name, tmp_alt, DFU_ALT_BUF_LEN);
685 strncat(buff, tmp_alt, DFU_ALT_BUF_LEN);
689 void set_dfu_alt_info(char *interface, char *devstr)
693 ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
695 if (env_get("dfu_alt_info"))
698 memset(buf, 0, sizeof(buf));
700 /* probe all MTD devices */
703 board_get_alt_info("ram", buf);
705 if (!uclass_get_device(UCLASS_MMC, 0, &dev))
706 board_get_alt_info("mmc0", buf);
708 if (!uclass_get_device(UCLASS_MMC, 1, &dev))
709 board_get_alt_info("mmc1", buf);
711 if (!uclass_get_device(UCLASS_SPI_FLASH, 0, &dev))
712 board_get_alt_info("nor0", buf);
714 env_set("dfu_alt_info", buf);
715 puts("DFU alt info setting: done\n");
719 static void board_copro_image_process(ulong fw_image, size_t fw_size)
721 int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */
723 if (!rproc_is_initialized())
725 printf("Remote Processor %d initialization failed\n",
730 ret = rproc_load(id, fw_image, fw_size);
731 printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
732 id, fw_image, fw_size, ret ? " Failed!" : " Success!");
736 env_set("copro_state", "booted");
740 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process);