board/dhelectronics/dh_imx6/dh_imx6_spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * DHCOM DH-iMX6 PDK SPL support
   4  *
   5  * Copyright (C) 2017 Marek Vasut <marex@denx.de>
   6  */
   7
   8 #include <common.h>
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/crm_regs.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/mx6-ddr.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/gpio.h>
  17 #include <asm/mach-imx/boot_mode.h>
  18 #include <asm/mach-imx/iomux-v3.h>
  19 #include <asm/mach-imx/mxc_i2c.h>
  20 #include <asm/io.h>
  21 #include <errno.h>
  22 #include <fuse.h>
  23 #include <fsl_esdhc.h>
  24 #include <i2c.h>
  25 #include <mmc.h>
  26 #include <spl.h>
  27
  28 #define ENET_PAD_CTRL                                                   \
  29         (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |  \
  30          PAD_CTL_HYS)
  31
  32 #define GPIO_PAD_CTRL                                                   \
  33         (PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
  34
  35 #define SPI_PAD_CTRL                                                    \
  36         (PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |          \
  37         PAD_CTL_SRE_FAST)
  38
  39 #define UART_PAD_CTRL                                                   \
  40         (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |  \
  41          PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  42
  43 #define USDHC_PAD_CTRL                                                  \
  44         (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |   \
  45          PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  46
  47 static const struct mx6dq_iomux_ddr_regs dhcom6dq_ddr_ioregs = {
  48         .dram_sdclk_0   = 0x00020030,
  49         .dram_sdclk_1   = 0x00020030,
  50         .dram_cas       = 0x00020030,
  51         .dram_ras       = 0x00020030,
  52         .dram_reset     = 0x00020030,
  53         .dram_sdcke0    = 0x00003000,
  54         .dram_sdcke1    = 0x00003000,
  55         .dram_sdba2     = 0x00000000,
  56         .dram_sdodt0    = 0x00003030,
  57         .dram_sdodt1    = 0x00003030,
  58         .dram_sdqs0     = 0x00000030,
  59         .dram_sdqs1     = 0x00000030,
  60         .dram_sdqs2     = 0x00000030,
  61         .dram_sdqs3     = 0x00000030,
  62         .dram_sdqs4     = 0x00000030,
  63         .dram_sdqs5     = 0x00000030,
  64         .dram_sdqs6     = 0x00000030,
  65         .dram_sdqs7     = 0x00000030,
  66         .dram_dqm0      = 0x00020030,
  67         .dram_dqm1      = 0x00020030,
  68         .dram_dqm2      = 0x00020030,
  69         .dram_dqm3      = 0x00020030,
  70         .dram_dqm4      = 0x00020030,
  71         .dram_dqm5      = 0x00020030,
  72         .dram_dqm6      = 0x00020030,
  73         .dram_dqm7      = 0x00020030,
  74 };
  75
  76 static const struct mx6dq_iomux_grp_regs dhcom6dq_grp_ioregs = {
  77         .grp_ddr_type   = 0x000C0000,
  78         .grp_ddrmode_ctl = 0x00020000,
  79         .grp_ddrpke     = 0x00000000,
  80         .grp_addds      = 0x00000030,
  81         .grp_ctlds      = 0x00000030,
  82         .grp_ddrmode    = 0x00020000,
  83         .grp_b0ds       = 0x00000030,
  84         .grp_b1ds       = 0x00000030,
  85         .grp_b2ds       = 0x00000030,
  86         .grp_b3ds       = 0x00000030,
  87         .grp_b4ds       = 0x00000030,
  88         .grp_b5ds       = 0x00000030,
  89         .grp_b6ds       = 0x00000030,
  90         .grp_b7ds       = 0x00000030,
  91 };
  92
  93 static const struct mx6sdl_iomux_ddr_regs dhcom6sdl_ddr_ioregs = {
  94         .dram_sdclk_0   = 0x00020030,
  95         .dram_sdclk_1   = 0x00020030,
  96         .dram_cas       = 0x00020030,
  97         .dram_ras       = 0x00020030,
  98         .dram_reset     = 0x00020030,
  99         .dram_sdcke0    = 0x00003000,
 100         .dram_sdcke1    = 0x00003000,
 101         .dram_sdba2     = 0x00000000,
 102         .dram_sdodt0    = 0x00003030,
 103         .dram_sdodt1    = 0x00003030,
 104         .dram_sdqs0     = 0x00000030,
 105         .dram_sdqs1     = 0x00000030,
 106         .dram_sdqs2     = 0x00000030,
 107         .dram_sdqs3     = 0x00000030,
 108         .dram_sdqs4     = 0x00000030,
 109         .dram_sdqs5     = 0x00000030,
 110         .dram_sdqs6     = 0x00000030,
 111         .dram_sdqs7     = 0x00000030,
 112         .dram_dqm0      = 0x00020030,
 113         .dram_dqm1      = 0x00020030,
 114         .dram_dqm2      = 0x00020030,
 115         .dram_dqm3      = 0x00020030,
 116         .dram_dqm4      = 0x00020030,
 117         .dram_dqm5      = 0x00020030,
 118         .dram_dqm6      = 0x00020030,
 119         .dram_dqm7      = 0x00020030,
 120 };
 121
 122 static const struct mx6sdl_iomux_grp_regs dhcom6sdl_grp_ioregs = {
 123         .grp_ddr_type   = 0x000C0000,
 124         .grp_ddrmode_ctl = 0x00020000,
 125         .grp_ddrpke     = 0x00000000,
 126         .grp_addds      = 0x00000030,
 127         .grp_ctlds      = 0x00000030,
 128         .grp_ddrmode    = 0x00020000,
 129         .grp_b0ds       = 0x00000030,
 130         .grp_b1ds       = 0x00000030,
 131         .grp_b2ds       = 0x00000030,
 132         .grp_b3ds       = 0x00000030,
 133         .grp_b4ds       = 0x00000030,
 134         .grp_b5ds       = 0x00000030,
 135         .grp_b6ds       = 0x00000030,
 136         .grp_b7ds       = 0x00000030,
 137 };
 138
 139 static const struct mx6_mmdc_calibration dhcom_mmdc_calib = {
 140         .p0_mpwldectrl0 = 0x0011000E,
 141         .p0_mpwldectrl1 = 0x000E001B,
 142         .p1_mpwldectrl0 = 0x00190015,
 143         .p1_mpwldectrl1 = 0x00070018,
 144         .p0_mpdgctrl0   = 0x42720306,
 145         .p0_mpdgctrl1   = 0x026F0266,
 146         .p1_mpdgctrl0   = 0x4273030A,
 147         .p1_mpdgctrl1   = 0x02740240,
 148         .p0_mprddlctl   = 0x45393B3E,
 149         .p1_mprddlctl   = 0x403A3747,
 150         .p0_mpwrdlctl   = 0x40434541,
 151         .p1_mpwrdlctl   = 0x473E4A3B,
 152 };
 153
 154 static const struct mx6_ddr3_cfg dhcom_mem_ddr = {
 155         .mem_speed      = 1600,
 156         .density        = 2,
 157         .width          = 64,
 158         .banks          = 8,
 159         .rowaddr        = 14,
 160         .coladdr        = 10,
 161         .pagesz         = 2,
 162         .trcd           = 1312,
 163         .trcmin         = 5863,
 164         .trasmin        = 3750,
 165 };
 166
 167 static const struct mx6_ddr_sysinfo dhcom_ddr_info = {
 168         /* width of data bus:0=16,1=32,2=64 */
 169         .dsize          = 2,
 170         .cs_density     = 16,
 171         .ncs            = 1,    /* single chip select */
 172         .cs1_mirror     = 1,
 173         .rtt_wr         = 1,    /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
 174         .rtt_nom        = 1,    /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
 175         .walat          = 1,    /* Write additional latency */
 176         .ralat          = 5,    /* Read additional latency */
 177         .mif3_mode      = 3,    /* Command prediction working mode */
 178         .bi_on          = 1,    /* Bank interleaving enabled */
 179         .sde_to_rst     = 0x10, /* 14 cycles, 200us (JEDEC default) */
 180         .rst_to_cke     = 0x23, /* 33 cycles, 500us (JEDEC default) */
 181         .refsel         = 1,    /* Refresh cycles at 32KHz */
 182         .refr           = 3,    /* 4 refresh commands per refresh cycle */
 183 };
 184
 185 static void ccgr_init(void)
 186 {
 187         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 188
 189         writel(0x00C03F3F, &ccm->CCGR0);
 190         writel(0x0030FC03, &ccm->CCGR1);
 191         writel(0x0FFFC000, &ccm->CCGR2);
 192         writel(0x3FF00000, &ccm->CCGR3);
 193         writel(0x00FFF300, &ccm->CCGR4);
 194         writel(0x0F0000C3, &ccm->CCGR5);
 195         writel(0x000003FF, &ccm->CCGR6);
 196 }
 197
 198 /* Board ID */
 199 static iomux_v3_cfg_t const hwcode_pads[] = {
 200         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 201         IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 202         IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 203 };
 204
 205 static void setup_iomux_boardid(void)
 206 {
 207         /* HW code pins: Setup alternate function and configure pads */
 208         SETUP_IOMUX_PADS(hwcode_pads);
 209 }
 210
 211 /* DDR Code */
 212 static iomux_v3_cfg_t const ddrcode_pads[] = {
 213         IOMUX_PADS(PAD_EIM_A16__GPIO2_IO22      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 214         IOMUX_PADS(PAD_EIM_A17__GPIO2_IO21      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 215 };
 216
 217 static void setup_iomux_ddrcode(void)
 218 {
 219         /* ddr code pins */
 220         SETUP_IOMUX_PADS(ddrcode_pads);
 221 }
 222
 223 enum dhcom_ddr3_code {
 224         DH_DDR3_SIZE_256MIB = 0x00,
 225         DH_DDR3_SIZE_512MIB = 0x01,
 226         DH_DDR3_SIZE_1GIB   = 0x02,
 227         DH_DDR3_SIZE_2GIB   = 0x03
 228 };
 229
 230 #define DDR3_CODE_BIT_0   IMX_GPIO_NR(2, 22)
 231 #define DDR3_CODE_BIT_1   IMX_GPIO_NR(2, 21)
 232
 233 enum dhcom_ddr3_code dhcom_get_ddr3_code(void)
 234 {
 235         enum dhcom_ddr3_code ddr3_code;
 236
 237         gpio_request(DDR3_CODE_BIT_0, "DDR3_CODE_BIT_0");
 238         gpio_request(DDR3_CODE_BIT_1, "DDR3_CODE_BIT_1");
 239
 240         gpio_direction_input(DDR3_CODE_BIT_0);
 241         gpio_direction_input(DDR3_CODE_BIT_1);
 242
 243         /* 256MB = 0b00; 512MB = 0b01; 1GB = 0b10; 2GB = 0b11 */
 244         ddr3_code = (!!gpio_get_value(DDR3_CODE_BIT_1) << 1)
 245              | (!!gpio_get_value(DDR3_CODE_BIT_0));
 246
 247         return ddr3_code;
 248 }
 249
 250 /* GPIO */
 251 static iomux_v3_cfg_t const gpio_pads[] = {
 252         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02       | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 253         IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04       | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 254         IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05       | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 255         IOMUX_PADS(PAD_CSI0_DAT17__GPIO6_IO03   | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 256         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 257         IOMUX_PADS(PAD_DI0_PIN4__GPIO4_IO20     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 258         IOMUX_PADS(PAD_EIM_D27__GPIO3_IO27      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 259         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 260         IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 261         IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14    | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 262         IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15    | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 263         IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 264         IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 265         IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 266         IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21   | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 267         IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 268         IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 269         IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 270         IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 271         IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19     | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 272         IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20      | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 273         IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18  | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 274         IOMUX_PADS(PAD_CSI0_MCLK__GPIO5_IO19    | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
 275 };
 276
 277 static void setup_iomux_gpio(void)
 278 {
 279         SETUP_IOMUX_PADS(gpio_pads);
 280 }
 281
 282 /* Ethernet */
 283 static iomux_v3_cfg_t const enet_pads[] = {
 284         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 285         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC       | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 286         IOMUX_PADS(PAD_ENET_TX_EN__ENET_TX_EN   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 287         IOMUX_PADS(PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 288         IOMUX_PADS(PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 289         IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 290         IOMUX_PADS(PAD_ENET_RX_ER__ENET_RX_ER   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 291         IOMUX_PADS(PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 292         IOMUX_PADS(PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 293         IOMUX_PADS(PAD_ENET_CRS_DV__ENET_RX_EN  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 294         /* SMSC PHY Reset */
 295         IOMUX_PADS(PAD_EIM_WAIT__GPIO5_IO00     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 296         /* ENET_VIO_GPIO */
 297         IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07       | MUX_PAD_CTRL(NO_PAD_CTRL)),
 298         /* ENET_Interrupt - (not used) */
 299         IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 300 };
 301
 302 static void setup_iomux_enet(void)
 303 {
 304         SETUP_IOMUX_PADS(enet_pads);
 305 }
 306
 307 /* SD interface */
 308 static iomux_v3_cfg_t const usdhc2_pads[] = {
 309         IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 310         IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 311         IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 312         IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 313         IOMUX_PADS(PAD_SD2_CLK__SD2_CLK         | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 314         IOMUX_PADS(PAD_SD2_CMD__SD2_CMD         | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 315         IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16    | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
 316 };
 317
 318 /* onboard microSD */
 319 static iomux_v3_cfg_t const usdhc3_pads[] = {
 320         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 321         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 322         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 323         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 324         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK         | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 325         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD         | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 326         IOMUX_PADS(PAD_SD3_RST__GPIO7_IO08      | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
 327 };
 328
 329 /* eMMC */
 330 static iomux_v3_cfg_t const usdhc4_pads[] = {
 331         IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 332         IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 333         IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 334         IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 335         IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 336         IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 337         IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 338         IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 339         IOMUX_PADS(PAD_SD4_CLK__SD4_CLK         | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 340         IOMUX_PADS(PAD_SD4_CMD__SD4_CMD         | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 341 };
 342
 343 /* SD */
 344 static void setup_iomux_sd(void)
 345 {
 346         SETUP_IOMUX_PADS(usdhc2_pads);
 347         SETUP_IOMUX_PADS(usdhc3_pads);
 348         SETUP_IOMUX_PADS(usdhc4_pads);
 349 }
 350
 351 /* SPI */
 352 static iomux_v3_cfg_t const ecspi1_pads[] = {
 353         /* SS0 */
 354         IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30      | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 355         IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO     | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 356         IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI     | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 357         IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK     | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 358 };
 359
 360 static void setup_iomux_spi(void)
 361 {
 362         SETUP_IOMUX_PADS(ecspi1_pads);
 363 }
 364
 365 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 366 {
 367         if (bus == 0 && cs == 0)
 368                 return IMX_GPIO_NR(2, 30);
 369         else
 370                 return -1;
 371 }
 372
 373 /* UART */
 374 static iomux_v3_cfg_t const uart1_pads[] = {
 375         IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 376         IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 377 };
 378
 379 static void setup_iomux_uart(void)
 380 {
 381         SETUP_IOMUX_PADS(uart1_pads);
 382 }
 383
 384 /* USB */
 385 static iomux_v3_cfg_t const usb_pads[] = {
 386         IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID       | MUX_PAD_CTRL(NO_PAD_CTRL)),
 387         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 388 };
 389
 390 static void setup_iomux_usb(void)
 391 {
 392         SETUP_IOMUX_PADS(usb_pads);
 393 }
 394
 395 void board_init_f(ulong dummy)
 396 {
 397         /* setup AIPS and disable watchdog */
 398         arch_cpu_init();
 399
 400         ccgr_init();
 401         gpr_init();
 402
 403         /* setup GP timer */
 404         timer_init();
 405
 406         setup_iomux_boardid();
 407         setup_iomux_ddrcode();
 408         setup_iomux_gpio();
 409         setup_iomux_enet();
 410         setup_iomux_sd();
 411         setup_iomux_spi();
 412         setup_iomux_uart();
 413         setup_iomux_usb();
 414
 415         /* UART clocks enabled and gd valid - init serial console */
 416         preloader_console_init();
 417
 418         /* Start the DDR DRAM */
 419         if (is_mx6dq())
 420                 mx6dq_dram_iocfg(dhcom_mem_ddr.width, &dhcom6dq_ddr_ioregs,
 421                                  &dhcom6dq_grp_ioregs);
 422         else
 423                 mx6sdl_dram_iocfg(dhcom_mem_ddr.width, &dhcom6sdl_ddr_ioregs,
 424                                   &dhcom6sdl_grp_ioregs);
 425         mx6_dram_cfg(&dhcom_ddr_info, &dhcom_mmdc_calib, &dhcom_mem_ddr);
 426
 427         /* Perform DDR DRAM calibration */
 428         udelay(100);
 429         mmdc_do_dqs_calibration(&dhcom_ddr_info);
 430
 431         /* Clear the BSS. */
 432         memset(__bss_start, 0, __bss_end - __bss_start);
 433
 434         /* load/boot image from boot device */
 435         board_init_r(NULL, 0);
 436 }