1 // SPDX-License-Identifier: GPL-2.0+
3 * DHCOM DH-iMX6 PDK board support
5 * Copyright (C) 2017 Marek Vasut <marex@denx.de>
10 #include <dm/device-internal.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/iomux.h>
15 #include <asm/arch/mx6-pins.h>
16 #include <asm/arch/sys_proto.h>
19 #include <asm/mach-imx/boot_mode.h>
20 #include <asm/mach-imx/iomux-v3.h>
21 #include <asm/mach-imx/mxc_i2c.h>
22 #include <asm/mach-imx/sata.h>
23 #include <environment.h>
25 #include <fsl_esdhc.h>
33 #include <usb/ehci-ci.h>
35 DECLARE_GLOBAL_DATA_PTR;
37 #define I2C_PAD_CTRL \
38 (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
39 PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
41 #define EEPROM_I2C_ADDRESS 0x50
43 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
45 static struct i2c_pads_info dh6sdl_i2c_pad_info0 = {
47 .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
48 .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
49 .gp = IMX_GPIO_NR(3, 21)
52 .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
53 .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
54 .gp = IMX_GPIO_NR(3, 28)
58 static struct i2c_pads_info dh6sdl_i2c_pad_info1 = {
60 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
61 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
62 .gp = IMX_GPIO_NR(4, 12)
65 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
66 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
67 .gp = IMX_GPIO_NR(4, 13)
71 static struct i2c_pads_info dh6sdl_i2c_pad_info2 = {
73 .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
74 .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
75 .gp = IMX_GPIO_NR(1, 3)
78 .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
79 .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
80 .gp = IMX_GPIO_NR(1, 6)
84 static struct i2c_pads_info dh6dq_i2c_pad_info0 = {
86 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
87 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
88 .gp = IMX_GPIO_NR(3, 21)
91 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
92 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
93 .gp = IMX_GPIO_NR(3, 28)
97 static struct i2c_pads_info dh6dq_i2c_pad_info1 = {
99 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
100 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
101 .gp = IMX_GPIO_NR(4, 12)
104 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
105 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
106 .gp = IMX_GPIO_NR(4, 13)
110 static struct i2c_pads_info dh6dq_i2c_pad_info2 = {
112 .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
113 .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
114 .gp = IMX_GPIO_NR(1, 3)
117 .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
118 .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
119 .gp = IMX_GPIO_NR(1, 6)
125 gd->ram_size = imx_ddr_size();
130 * Do not overwrite the console
131 * Use always serial for U-Boot console
133 int overwrite_console(void)
138 #ifdef CONFIG_FEC_MXC
139 static void eth_phy_reset(void)
142 gpio_direction_output(IMX_GPIO_NR(5, 0) , 0);
144 gpio_set_value(IMX_GPIO_NR(5, 0), 1);
147 gpio_direction_output(IMX_GPIO_NR(1, 7) , 0);
150 * KSZ9021 PHY needs at least 10 mSec after PHY reset
151 * is released to stabilize
156 static int setup_fec_clock(void)
158 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
160 /* set gpr1[21] to select anatop clock */
161 clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21);
163 return enable_fec_anatop_clock(0, ENET_50MHZ);
166 int board_eth_init(bd_t *bis)
168 uint32_t base = IMX_FEC_BASE;
169 struct mii_dev *bus = NULL;
170 struct phy_device *phydev = NULL;
172 gpio_request(IMX_GPIO_NR(5, 0), "PHY-reset");
173 gpio_request(IMX_GPIO_NR(1, 7), "VIO");
179 bus = fec_get_miibus(base, -1);
184 phydev = phy_find_by_mask(bus, 0xf, PHY_INTERFACE_MODE_RGMII);
186 printf("Ethernet PHY not found!\n");
190 return fec_probe(bis, -1, base, bus, phydev);
194 #ifdef CONFIG_USB_EHCI_MX6
195 static void setup_usb(void)
197 gpio_request(IMX_GPIO_NR(3, 31), "USB-VBUS");
199 * Set daisy chain for otg_pin_id on MX6Q.
200 * For MX6DL, this bit is reserved.
202 imx_iomux_set_gpr_register(1, 13, 1, 0);
205 int board_usb_phy_mode(int port)
208 return USB_INIT_HOST;
210 return USB_INIT_DEVICE;
213 int board_ehci_power(int port, int on)
219 gpio_direction_output(IMX_GPIO_NR(3, 31), !!on);
222 printf("MXC USB port %d not yet supported\n", port);
230 static int setup_dhcom_mac_from_fuse(void)
232 unsigned char enetaddr[6];
235 ret = eth_env_get_enetaddr("ethaddr", enetaddr);
236 if (ret) /* ethaddr is already set */
239 imx_get_mac_from_fuse(0, enetaddr);
241 if (is_valid_ethaddr(enetaddr)) {
242 eth_env_set_enetaddr("ethaddr", enetaddr);
246 ret = i2c_set_bus_num(2);
248 printf("Error switching I2C bus!\n");
252 ret = i2c_read(EEPROM_I2C_ADDRESS, 0xfa, 0x1, enetaddr, 0x6);
254 printf("Error reading configuration EEPROM!\n");
258 if (is_valid_ethaddr(enetaddr))
259 eth_env_set_enetaddr("ethaddr", enetaddr);
264 int board_early_init_f(void)
266 #ifdef CONFIG_USB_EHCI_MX6
273 #ifdef CONFIG_MXC_SPI
274 int board_spi_cs_gpio(unsigned bus, unsigned cs)
276 if (bus == 0 && cs == 0)
277 return IMX_GPIO_NR(2, 30);
285 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
287 /* address of boot parameters */
288 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
290 /* Enable eim_slow clocks */
291 setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
293 #ifdef CONFIG_SYS_I2C_MXC
295 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info0);
296 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info1);
297 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info2);
299 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info0);
300 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info1);
301 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info2);
309 setup_dhcom_mac_from_fuse();
314 #ifdef CONFIG_CMD_BMODE
315 static const struct boot_mode board_boot_modes[] = {
316 /* 4 bit bus width */
317 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
318 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
319 /* 8 bit bus width */
320 {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
325 #define HW_CODE_BIT_0 IMX_GPIO_NR(2, 19)
326 #define HW_CODE_BIT_1 IMX_GPIO_NR(6, 6)
327 #define HW_CODE_BIT_2 IMX_GPIO_NR(2, 16)
329 static int board_get_hwcode(void)
333 gpio_request(HW_CODE_BIT_0, "HW-code-bit-0");
334 gpio_request(HW_CODE_BIT_1, "HW-code-bit-1");
335 gpio_request(HW_CODE_BIT_2, "HW-code-bit-2");
337 gpio_direction_input(HW_CODE_BIT_0);
338 gpio_direction_input(HW_CODE_BIT_1);
339 gpio_direction_input(HW_CODE_BIT_2);
341 /* HW 100 + HW 200 = 00b; HW 300 = 01b */
342 hw_code = ((gpio_get_value(HW_CODE_BIT_2) << 2) |
343 (gpio_get_value(HW_CODE_BIT_1) << 1) |
344 gpio_get_value(HW_CODE_BIT_0)) + 2;
349 int board_late_init(void)
354 hw_code = board_get_hwcode();
356 switch (get_cpu_type()) {
357 case MXC_CPU_MX6SOLO:
358 snprintf(buf, sizeof(buf), "imx6s-dhcom%1d", hw_code);
361 snprintf(buf, sizeof(buf), "imx6dl-dhcom%1d", hw_code);
364 snprintf(buf, sizeof(buf), "imx6d-dhcom%1d", hw_code);
367 snprintf(buf, sizeof(buf), "imx6q-dhcom%1d", hw_code);
370 snprintf(buf, sizeof(buf), "UNKNOWN%1d", hw_code);
374 env_set("dhcom", buf);
376 #ifdef CONFIG_CMD_BMODE
377 add_board_boot_modes(board_boot_modes);
384 puts("Board: DHCOM i.MX6\n");