2 * Copyright (C) 2015 Marek Vasut <marex@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/at91_common.h>
10 #include <asm/arch/at91_pmc.h>
11 #include <asm/arch/at91_rstc.h>
12 #include <asm/arch/atmel_mpddrc.h>
13 #include <asm/arch/atmel_usba_udc.h>
14 #include <asm/arch/gpio.h>
15 #include <asm/arch/clk.h>
16 #include <asm/arch/sama5d3_smc.h>
17 #include <asm/arch/sama5d4.h>
18 #include <atmel_hlcdc.h>
19 #include <atmel_mci.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 #ifdef CONFIG_ATMEL_SPI
30 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
32 return bus == 0 && cs == 0;
35 void spi_cs_activate(struct spi_slave *slave)
37 at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
40 void spi_cs_deactivate(struct spi_slave *slave)
42 at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
45 static void ma5d4evk_spi0_hw_init(void)
47 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */
48 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */
49 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */
51 at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */
54 at91_periph_clk_enable(ATMEL_ID_SPI0);
56 #endif /* CONFIG_ATMEL_SPI */
59 static void ma5d4evk_usb_hw_init(void)
61 at91_set_pio_output(AT91_PIO_PORTE, 11, 0);
62 at91_set_pio_output(AT91_PIO_PORTE, 14, 0);
67 vidinfo_t panel_info = {
75 .vl_right_margin = 164,
77 .vl_upper_margin = 23,
78 .vl_lower_margin = 10,
79 .mmio = ATMEL_BASE_LCDC,
82 /* No power up/down pin for the LCD pannel */
83 void lcd_enable(void) { /* Empty! */ }
84 void lcd_disable(void) { /* Empty! */ }
86 unsigned int has_lcdc(void)
91 static void ma5d4evk_lcd_hw_init(void)
93 at91_set_a_periph(AT91_PIO_PORTA, 24, 1); /* LCDPWM */
94 at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
95 at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
96 at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
97 at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
98 at91_set_a_periph(AT91_PIO_PORTA, 29, 1); /* LCDDEN */
100 at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */
101 at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */
102 at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
103 at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
104 at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
105 at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
106 at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
107 at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
109 at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */
110 at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */
111 at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
112 at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
113 at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
114 at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
115 at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
116 at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
118 at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */
119 at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */
120 at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */
121 at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */
122 at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */
123 at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */
124 at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */
125 at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */
128 at91_periph_clk_enable(ATMEL_ID_LCDC);
131 #endif /* CONFIG_LCD */
133 #ifdef CONFIG_GENERIC_ATMEL_MCI
135 void ma5d4evk_mci0_hw_init(void)
137 at91_set_b_periph(AT91_PIO_PORTC, 5, 1); /* MCI1 CDA */
138 at91_set_b_periph(AT91_PIO_PORTC, 6, 1); /* MCI1 DA0 */
139 at91_set_b_periph(AT91_PIO_PORTC, 7, 1); /* MCI1 DA1 */
140 at91_set_b_periph(AT91_PIO_PORTC, 8, 1); /* MCI1 DA2 */
141 at91_set_b_periph(AT91_PIO_PORTC, 9, 1); /* MCI1 DA3 */
142 at91_set_b_periph(AT91_PIO_PORTC, 10, 1); /* MCI1 DA4 */
143 at91_set_b_periph(AT91_PIO_PORTC, 11, 1); /* MCI1 DA5 */
144 at91_set_b_periph(AT91_PIO_PORTC, 12, 1); /* MCI1 DA6 */
145 at91_set_b_periph(AT91_PIO_PORTC, 13, 1); /* MCI1 DA7 */
146 at91_set_b_periph(AT91_PIO_PORTC, 4, 0); /* MCI1 CLK */
149 * As the mci io internal pull down is too strong, so if the io needs
150 * external pull up, the pull up resistor will be very small, if so
151 * the power consumption will increase, so disable the internal pull
152 * down to save the power.
154 at91_set_pio_pulldown(AT91_PIO_PORTC, 5, 0);
155 at91_set_pio_pulldown(AT91_PIO_PORTC, 6, 0);
156 at91_set_pio_pulldown(AT91_PIO_PORTC, 7, 0);
157 at91_set_pio_pulldown(AT91_PIO_PORTC, 8, 0);
158 at91_set_pio_pulldown(AT91_PIO_PORTC, 9, 0);
159 at91_set_pio_pulldown(AT91_PIO_PORTC, 10, 0);
160 at91_set_pio_pulldown(AT91_PIO_PORTC, 11, 0);
161 at91_set_pio_pulldown(AT91_PIO_PORTC, 12, 0);
162 at91_set_pio_pulldown(AT91_PIO_PORTC, 13, 0);
163 at91_set_pio_pulldown(AT91_PIO_PORTC, 4, 0);
166 at91_periph_clk_enable(ATMEL_ID_MCI0);
169 /* On-board MicroSD slot */
170 void ma5d4evk_mci1_hw_init(void)
172 at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */
173 at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */
174 at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */
175 at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */
176 at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */
177 at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */
180 * As the mci io internal pull down is too strong, so if the io needs
181 * external pull up, the pull up resistor will be very small, if so
182 * the power consumption will increase, so disable the internal pull
183 * down to save the power.
185 at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
186 at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
187 at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
188 at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
189 at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
190 at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
192 /* Deal with WP pin on the microSD slot. */
193 at91_set_pio_output(AT91_PIO_PORTE, 16, 0);
194 at91_set_pio_pulldown(AT91_PIO_PORTE, 16, 1);
197 at91_periph_clk_enable(ATMEL_ID_MCI1);
200 int board_mmc_init(bd_t *bis)
204 /* De-assert reset on On-SoM eMMC */
205 at91_set_pio_output(AT91_PIO_PORTE, 15, 1);
206 at91_set_pio_pulldown(AT91_PIO_PORTE, 15, 0);
208 ret = atmel_mci_init((void *)ATMEL_BASE_MCI0);
209 if (ret) /* eMMC init failed, skip it. */
210 at91_set_pio_output(AT91_PIO_PORTE, 15, 0);
212 /* Enable the power supply to On-board MicroSD */
213 at91_set_pio_output(AT91_PIO_PORTE, 17, 0);
215 ret = atmel_mci_init((void *)ATMEL_BASE_MCI1);
216 if (ret) /* uSD init failed, power it down. */
217 at91_set_pio_output(AT91_PIO_PORTE, 17, 1);
221 #endif /* CONFIG_GENERIC_ATMEL_MCI */
224 void ma5d4evk_macb0_hw_init(void)
226 at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */
227 at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */
228 at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */
229 at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */
230 at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */
231 at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */
232 at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */
233 at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */
234 at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */
235 at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */
238 at91_periph_clk_enable(ATMEL_ID_GMAC0);
242 static void ma5d4evk_serial_hw_init(void)
245 at91_set_a_periph(AT91_PIO_PORTD, 13, 1); /* TXD */
246 at91_set_a_periph(AT91_PIO_PORTD, 12, 0); /* RXD */
247 at91_set_a_periph(AT91_PIO_PORTD, 11, 0); /* RTS */
248 at91_set_a_periph(AT91_PIO_PORTD, 10, 0); /* CTS */
249 at91_periph_clk_enable(ATMEL_ID_USART0);
252 at91_set_a_periph(AT91_PIO_PORTD, 17, 1); /* TXD */
253 at91_set_a_periph(AT91_PIO_PORTD, 16, 0); /* RXD */
254 at91_set_a_periph(AT91_PIO_PORTD, 15, 0); /* RTS */
255 at91_set_a_periph(AT91_PIO_PORTD, 14, 0); /* CTS */
256 at91_periph_clk_enable(ATMEL_ID_USART1);
259 int board_early_init_f(void)
261 at91_periph_clk_enable(ATMEL_ID_PIOA);
262 at91_periph_clk_enable(ATMEL_ID_PIOB);
263 at91_periph_clk_enable(ATMEL_ID_PIOC);
264 at91_periph_clk_enable(ATMEL_ID_PIOD);
265 at91_periph_clk_enable(ATMEL_ID_PIOE);
267 /* Configure LEDs as OFF */
268 at91_set_pio_output(AT91_PIO_PORTD, 28, 0);
269 at91_set_pio_output(AT91_PIO_PORTD, 29, 0);
270 at91_set_pio_output(AT91_PIO_PORTD, 30, 0);
272 /* Reset CAN controllers */
273 at91_set_pio_output(AT91_PIO_PORTB, 21, 0);
275 at91_set_pio_output(AT91_PIO_PORTB, 21, 1);
276 at91_set_pio_pulldown(AT91_PIO_PORTB, 21, 0);
278 ma5d4evk_serial_hw_init();
285 /* adress of boot parameters */
286 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
288 #ifdef CONFIG_ATMEL_SPI
289 ma5d4evk_spi0_hw_init();
291 #ifdef CONFIG_GENERIC_ATMEL_MCI
292 ma5d4evk_mci0_hw_init();
293 ma5d4evk_mci1_hw_init();
296 ma5d4evk_macb0_hw_init();
299 ma5d4evk_lcd_hw_init();
301 #ifdef CONFIG_CMD_USB
302 ma5d4evk_usb_hw_init();
304 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
313 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
314 CONFIG_SYS_SDRAM_SIZE);
318 int board_eth_init(bd_t *bis)
323 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00);
326 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
327 usba_udc_probe(&pdata);
328 #ifdef CONFIG_USB_ETH_RNDIS
329 usb_eth_initialize(bis);
337 #ifdef CONFIG_SPL_BUILD
338 void spl_board_init(void)
340 ma5d4evk_spi0_hw_init();
343 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
345 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
347 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
348 ATMEL_MPDDRC_CR_NR_ROW_13 |
349 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
350 ATMEL_MPDDRC_CR_NB_8BANKS |
351 ATMEL_MPDDRC_CR_NDQS_DISABLED |
352 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
353 ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
357 ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
358 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
359 3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
360 10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
361 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
362 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
363 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
364 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
366 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
367 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
368 25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
369 23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
371 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
372 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
373 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
374 2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
375 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
380 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
381 struct atmel_mpddrc_config ddr2;
385 /* enable MPDDR clock */
386 at91_periph_clk_enable(ATMEL_ID_MPDDRC);
387 writel(AT91_PMC_DDR, &pmc->scer);
389 /* DDRAM2 Controller initialize */
390 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
393 void at91_pmc_init(void)
395 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
398 tmp = AT91_PMC_PLLAR_29 |
399 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
400 AT91_PMC_PLLXR_MUL(87) |
401 AT91_PMC_PLLXR_DIV(1);
404 writel(0x0 << 8, &pmc->pllicpr);
406 tmp = AT91_PMC_MCKR_H32MXDIV |
407 AT91_PMC_MCKR_PLLADIV_2 |
408 AT91_PMC_MCKR_MDIV_3 |
409 AT91_PMC_MCKR_CSS_PLLA;