2 * (C) Copyright 2006 DENX Software Engineering
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #if defined(CONFIG_CMD_NAND)
26 #if !defined(CONFIG_NAND_LEGACY)
29 #include <asm/arch/pxa-regs.h>
31 #ifdef CONFIG_SYS_DFC_DEBUG1
32 # define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
34 # define DFC_DEBUG1(fmt, args...)
37 #ifdef CONFIG_SYS_DFC_DEBUG2
38 # define DFC_DEBUG2(fmt, args...) printf(fmt, ##args)
40 # define DFC_DEBUG2(fmt, args...)
43 #ifdef CONFIG_SYS_DFC_DEBUG3
44 # define DFC_DEBUG3(fmt, args...) printf(fmt, ##args)
46 # define DFC_DEBUG3(fmt, args...)
49 /* These really don't belong here, as they are specific to the NAND Model */
50 static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
52 static struct nand_bbt_descr delta_bbt_descr = {
56 .pattern = scan_ff_pattern
59 static struct nand_ecclayout delta_oob = {
61 .eccpos = {2, 3, 4, 5, 6, 7},
62 .oobfree = { {8, 2}, {12, 4} }
66 * not required for Monahans DFC
68 static void dfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
74 /* read device ready pin */
75 static int dfc_device_ready(struct mtd_info *mtdinfo)
86 * Write buf to the DFC Controller Data Buffer
88 static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
90 unsigned long bytes_multi = len & 0xfffffffc;
91 unsigned long rest = len & 0x3;
92 unsigned long *long_buf;
95 DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf));
97 for(i=0; i<bytes_multi; i+=4) {
98 long_buf = (unsigned long*) &buf[i];
103 printf("dfc_write_buf: ERROR, writing non 4-byte aligned data.\n");
109 static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
113 /* we have to be carefull not to overflow the buffer if len is
114 * not a multiple of 4 */
115 unsigned long bytes_multi = len & 0xfffffffc;
116 unsigned long rest = len & 0x3;
117 unsigned long *long_buf;
119 DFC_DEBUG3("dfc_read_buf: reading %d bytes.\n", len);
120 /* if there are any, first copy multiple of 4 bytes */
122 for(i=0; i<bytes_multi; i+=4) {
123 long_buf = (unsigned long*) &buf[i];
128 /* ...then the rest */
130 unsigned long rest_data = NDDB;
132 buf[i+j] = (u_char) ((rest_data>>j) & 0xff);
139 * read a word. Not implemented as not used in NAND code.
141 static u16 dfc_read_word(struct mtd_info *mtd)
143 printf("dfc_read_word: UNIMPLEMENTED.\n");
147 /* global var, too bad: mk@tbd: move to ->priv pointer */
148 static unsigned long read_buf = 0;
149 static int bytes_read = -1;
152 * read a byte from NDDB Because we can only read 4 bytes from NDDB at
153 * a time, we buffer the remaining bytes. The buffer is reset when a
154 * new command is sent to the chip.
157 * This function is currently only used to read status and id
158 * bytes. For these commands always 8 bytes need to be read from
159 * NDDB. So we read and discard these bytes right now. In case this
160 * function is used for anything else in the future, we must check
161 * what was the last command issued and read the appropriate amount of
162 * bytes respectively.
164 static u_char dfc_read_byte(struct mtd_info *mtd)
174 byte = (unsigned char) (read_buf>>(8 * bytes_read++));
178 DFC_DEBUG2("dfc_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read - 1, byte, read_buf);
182 /* calculate delta between OSCR values start and now */
183 static unsigned long get_delta(unsigned long start)
185 unsigned long cur = OSCR;
187 if(cur < start) /* OSCR overflowed */
188 return (cur + (start^0xffffffff));
190 return (cur - start);
193 /* delay function, this doesn't belong here */
194 static void wait_us(unsigned long us)
196 unsigned long start = OSCR;
199 while (get_delta(start) < us) {
204 static void dfc_clear_nddb(void)
206 NDCR &= ~NDCR_ND_RUN;
207 wait_us(CONFIG_SYS_NAND_OTHER_TO);
210 /* wait_event with timeout */
211 static unsigned long dfc_wait_event(unsigned long event)
213 unsigned long ndsr, timeout, start = OSCR;
217 else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
218 timeout = CONFIG_SYS_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ;
220 timeout = CONFIG_SYS_NAND_OTHER_TO * OSCR_CLK_FREQ;
228 if(get_delta(start) > timeout) {
229 DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%lx.\n", event);
237 /* we don't always wan't to do this */
238 static void dfc_new_cmd(void)
241 unsigned long status;
243 while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) {
247 /* set NDCR[NDRUN] */
248 if(!(NDCR & NDCR_ND_RUN))
251 status = dfc_wait_event(NDSR_WRCMDREQ);
253 if(status & NDSR_WRCMDREQ)
256 DFC_DEBUG2("dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry);
259 DFC_DEBUG1("dfc_new_cmd: giving up after %d retries.\n", retry);
262 /* this function is called after Programm and Erase Operations to
263 * check for success or failure */
264 static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this)
266 unsigned long ndsr=0, event=0;
267 int state = this->state;
269 if(state == FL_WRITING) {
270 event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
271 } else if(state == FL_ERASING) {
272 event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
275 ndsr = dfc_wait_event(event);
277 if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000))
278 return(0x1); /* Status Read error */
282 /* cmdfunc send commands to the DFC */
283 static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
284 int column, int page_addr)
286 /* register struct nand_chip *this = mtd->priv; */
287 unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0;
289 /* clear the ugly byte read buffer */
295 DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
297 ndcb0 = (NAND_CMD_READ0 | (4<<16));
298 column >>= 1; /* adjust for 16 bit bus */
299 ndcb1 = (((column>>1) & 0xff) |
300 ((page_addr<<8) & 0xff00) |
301 ((page_addr<<8) & 0xff0000) |
302 ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
306 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READ1 unimplemented!\n");
308 case NAND_CMD_READOOB:
309 DFC_DEBUG1("dfc_cmdfunc: NAND_CMD_READOOB unimplemented!\n");
311 case NAND_CMD_READID:
313 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READID.\n");
314 ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/
317 case NAND_CMD_PAGEPROG:
318 /* sent as a multicommand in NAND_CMD_SEQIN */
319 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n");
321 case NAND_CMD_ERASE1:
322 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE1, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
324 ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16));
325 ndcb1 = (page_addr & 0x00ffffff);
327 case NAND_CMD_ERASE2:
328 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n");
331 /* send PAGE_PROG command(0x1080) */
333 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
334 ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16));
335 column >>= 1; /* adjust for 16 bit bus */
336 ndcb1 = (((column>>1) & 0xff) |
337 ((page_addr<<8) & 0xff00) |
338 ((page_addr<<8) & 0xff0000) |
339 ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
342 case NAND_CMD_STATUS:
343 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_STATUS.\n");
345 ndcb0 = NAND_CMD_STATUS | (4<<21);
349 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_RESET.\n");
350 ndcb0 = NAND_CMD_RESET | (5<<21);
351 event = NDSR_CS0_CMDD;
354 printk("dfc_cmdfunc: error, unsupported command.\n");
364 dfc_wait_event(event);
369 static void dfc_gpio_init(void)
371 DFC_DEBUG2("Setting up DFC GPIO's.\n");
373 /* no idea what is done here, see zylonite.c */
376 DF_ALE_WE1 = 0x00000001;
377 DF_ALE_WE2 = 0x00000001;
378 DF_nCS0 = 0x00000001;
379 DF_nCS1 = 0x00000001;
387 DF_IO10 = 0x00000001;
389 DF_IO11 = 0x00000001;
391 DF_IO12 = 0x00000001;
393 DF_IO13 = 0x00000001;
395 DF_IO14 = 0x00000001;
397 DF_IO15 = 0x00000001;
407 * Board-specific NAND initialization. The following members of the
408 * argument are board-specific (per include/linux/mtd/nand_new.h):
409 * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
410 * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
411 * - hwcontrol: hardwarespecific function for accesing control-lines
412 * - dev_ready: hardwarespecific function for accesing device ready/busy line
413 * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
414 * only be provided if a hardware ECC is available
415 * - ecc.mode: mode of ecc, see defines
416 * - chip_delay: chip dependent delay for transfering data from array to
418 * - options: various chip options. They can partly be set to inform
419 * nand_scan about special functionality. See the defines for further
421 * Members with a "?" were not set in the merged testing-NAND branch,
422 * so they are not set here either.
424 int board_nand_init(struct nand_chip *nand)
426 unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
428 /* set up GPIO Control Registers */
431 /* turn on the NAND Controller Clock (104 MHz @ D0) */
432 CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
434 #undef CONFIG_SYS_TIMING_TIGHT
435 #ifndef CONFIG_SYS_TIMING_TIGHT
436 tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
438 tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
440 tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1),
442 tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1),
444 tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1),
446 tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1),
448 tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1),
450 tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1),
452 tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1),
454 #else /* this is the tight timing */
456 tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)),
458 tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)),
460 tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)),
462 tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)),
464 tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)),
466 tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)),
468 tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2),
470 tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2),
472 tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2),
474 #endif /* CONFIG_SYS_TIMING_TIGHT */
477 DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR);
479 /* tRP value is split in the register */
487 NDTR0CS0 = (tCH << 19) |
495 NDTR1CS0 = (tR << 16) |
499 /* If it doesn't work (unlikely) think about:
501 * - chip select don't care
502 * - read id byte count
504 * Intentionally enabled by not setting bits:
507 * - cs don't care, see if we can enable later!
508 * - row address start position (after second cycle)
509 * - pages per block = 32
510 * - ND_RDY : clears command buffer
512 /* NDCR_NCSX | /\* Chip select busy don't care *\/ */
514 NDCR = (NDCR_SPARE_EN | /* use the spare area */
515 NDCR_DWIDTH_C | /* 16bit DFC data bus width */
516 NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
517 (2 << 16) | /* read id count = 7 ???? mk@tbd */
518 NDCR_ND_ARB_EN | /* enable bus arbiter */
519 NDCR_RDYM | /* flash device ready ir masked */
520 NDCR_CS0_PAGEDM | /* ND_nCSx page done ir masked */
522 NDCR_CS0_CMDDM | /* ND_CSx command done ir masked */
524 NDCR_CS0_BBDM | /* ND_CSx bad block detect ir masked */
526 NDCR_DBERRM | /* double bit error ir masked */
527 NDCR_SBERRM | /* single bit error ir masked */
528 NDCR_WRDREQM | /* write data request ir masked */
529 NDCR_RDDREQM | /* read data request ir masked */
530 NDCR_WRCMDREQM); /* write command request ir masked */
533 /* wait 10 us due to cmd buffer clear reset */
537 nand->cmd_ctrl = dfc_hwcontrol;
538 /* nand->dev_ready = dfc_device_ready; */
539 nand->ecc.mode = NAND_ECC_SOFT;
540 nand->ecc.layout = &delta_oob;
541 nand->options = NAND_BUSWIDTH_16;
542 nand->waitfunc = dfc_wait;
543 nand->read_byte = dfc_read_byte;
544 nand->read_word = dfc_read_word;
545 nand->read_buf = dfc_read_buf;
546 nand->write_buf = dfc_write_buf;
548 nand->cmdfunc = dfc_cmdfunc;
549 nand->badblock_pattern = &delta_bbt_descr;
554 #error "U-Boot legacy NAND support not available for Monahans DFC."