1 /* Memory sub-system initialization code */
5 #include <asm/regdef.h>
6 #include <asm/au1x00.h>
7 #include <asm/mipsregs.h>
9 #define AU1500_SYS_ADDR 0xB1900000
10 #define sys_endian 0x0038
11 #define CP0_Config0 $16
12 #define MEM_1MS ((396000000/1000000) * 1000)
21 * Step 1) Establish CPU endian mode.
23 * Switch S1.1 Off(bit7 reads 1) is Little Endian
24 * Switch S1.1 On (bit7 reads 0) is Big Endian
41 beq zero,t1,big_endian
45 /* Change Au1 core to little endian */
46 li t0, AU1500_SYS_ADDR
54 /* Big Endian is default so nothing to do but fall through */
59 * Step 2) Establish Status Register
60 * (set BEV, clear ERL, clear EXL, clear IE)
66 * Step 3) Establish CP0 Config0
73 * Step 4) Disable Watchpoint facilities
79 * Step 5) Disable the performance counters
81 mtc0 zero, CP0_PERFORMANCE
85 * Step 6) Establish EJTAG Debug register
91 * Step 7) Establish Cause
97 /* Establish Wired (and Random) */
101 /* First setup pll:s to make serial work ok */
102 /* We have a 12 MHz crystal */
104 li t1, 0x21 /* 396 MHz */
110 /* wait 1mS for clocks to settle */
117 li t1, 0x20 /* 96 MHz */
118 sw t1, 0(t0) /* aux pll */
121 /* Static memory controller */
123 /* RCE0 AMD 29LV640M MirrorBit Flash */
136 /* RCE1 CPLD Board Logic */
149 /* RCE2 CPLD Board Logic */
162 /* RCE3 PCMCIA 250ns */
177 /* Set peripherals to a known state */
203 li t0, IC0_FALLINGCLR
236 li t0, IC1_FALLINGCLR
256 li t0, SYS_PININPUTEN
278 /* wait 1mS before setup */
313 li t1, 0x64000C24 /* Disable */
328 li t1, 0x66000C24 /* Enable */
342 /* wait 1mS after setup */