2 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
4 * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
5 * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
7 * Parts are shamelessly stolen from various TI sources, original copyright
10 * Copyright (C) 2004 Texas Instruments.
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
32 #include <asm/arch/hardware.h>
33 #include <asm/arch/emac_defs.h>
35 #define DAVINCI_A3CR (0x01E00014) /* EMIF-A CS3 config register. */
36 #define DAVINCI_A3CR_VAL (0x3FFFFFFD) /* EMIF-A CS3 value for FPGA. */
38 #define INTEGRITY_SYSCFG_OFFSET 0x7E8
39 #define INTEGRITY_CHECKWORD_OFFSET 0x7F8
40 #define INTEGRITY_CHECKWORD_VALUE 0x10ADBEEF
42 DECLARE_GLOBAL_DATA_PTR;
44 extern void timer_init(void);
45 extern int eth_hw_init(void);
48 /* Works on Always On power domain only (no PD argument) */
49 void lpsc_on(unsigned int id)
51 dv_reg_p mdstat, mdctl;
53 if (id >= DAVINCI_LPSC_GEM)
54 return; /* Don't work on DSP Power Domain */
56 mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
57 mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
59 while (REG(PSC_PTSTAT) & 0x01);
61 if ((*mdstat & 0x1f) == 0x03)
62 return; /* Already on and enabled */
66 /* Special treatment for some modules as for sprue14 p.7.4.2 */
68 case DAVINCI_LPSC_VPSSSLV:
69 case DAVINCI_LPSC_EMAC:
70 case DAVINCI_LPSC_EMAC_WRAPPER:
71 case DAVINCI_LPSC_MDIO:
72 case DAVINCI_LPSC_USB:
73 case DAVINCI_LPSC_ATA:
74 case DAVINCI_LPSC_VLYNQ:
75 case DAVINCI_LPSC_UHPI:
76 case DAVINCI_LPSC_DDR_EMIF:
77 case DAVINCI_LPSC_AEMIF:
78 case DAVINCI_LPSC_MMC_SD:
79 case DAVINCI_LPSC_MEMSTICK:
80 case DAVINCI_LPSC_McBSP:
81 case DAVINCI_LPSC_GPIO:
86 REG(PSC_PTCMD) = 0x01;
88 while (REG(PSC_PTSTAT) & 0x03);
89 while ((*mdstat & 0x1f) != 0x03); /* Probably an overkill... */
92 #if !defined(CFG_USE_DSPLINK)
97 if (REG(PSC_PDSTAT1) & 0x1f)
98 return; /* Already on */
100 REG(PSC_GBLCTL) |= 0x01;
101 REG(PSC_PDCTL1) |= 0x01;
102 REG(PSC_PDCTL1) &= ~0x100;
103 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
104 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
105 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
106 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
107 REG(PSC_PTCMD) = 0x02;
109 for (i = 0; i < 100; i++) {
110 if (REG(PSC_EPCPR) & 0x02)
114 REG(PSC_CHP_SHRTSW) = 0x01;
115 REG(PSC_PDCTL1) |= 0x100;
116 REG(PSC_EPCCR) = 0x02;
118 for (i = 0; i < 100; i++) {
119 if (!(REG(PSC_PTSTAT) & 0x02))
123 REG(PSC_GBLCTL) &= ~0x1f;
125 #endif /* CFG_USE_DSPLINK */
129 /* arch number of the board */
130 gd->bd->bi_arch_number = MACH_TYPE_SFFSDR;
132 /* address of boot parameters */
133 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
135 /* Workaround for TMS320DM6446 errata 1.3.22 */
136 REG(PSC_SILVER_BULLET) = 0;
138 /* Power on required peripherals */
139 lpsc_on(DAVINCI_LPSC_EMAC);
140 lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
141 lpsc_on(DAVINCI_LPSC_MDIO);
142 lpsc_on(DAVINCI_LPSC_I2C);
143 lpsc_on(DAVINCI_LPSC_UART0);
144 lpsc_on(DAVINCI_LPSC_TIMER1);
145 lpsc_on(DAVINCI_LPSC_GPIO);
147 #if !defined(CFG_USE_DSPLINK)
148 /* Powerup the DSP */
150 #endif /* CFG_USE_DSPLINK */
152 /* Bringup UART0 out of reset */
153 REG(UART0_PWREMU_MGMT) = 0x0000e003;
155 /* Enable GIO3.3V cells used for EMAC */
156 REG(VDD3P3V_PWDN) = 0;
158 /* Enable UART0 MUX lines */
161 /* Enable EMAC and AEMIF pins */
162 REG(PINMUX0) = 0x80000c1f;
164 /* Enable I2C pin Mux */
165 REG(PINMUX1) |= (1 << 7);
167 /* Set the Bus Priority Register to appropriate value */
175 /* Read ethernet MAC address from Integrity data structure inside EEPROM. */
176 int read_mac_address(uint8_t *buf)
178 u_int32_t value, mac[2], address;
180 /* Read Integrity data structure checkword. */
181 if (i2c_read(CFG_I2C_EEPROM_ADDR, INTEGRITY_CHECKWORD_OFFSET,
182 CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
184 if (value != INTEGRITY_CHECKWORD_VALUE)
187 /* Read SYSCFG structure offset. */
188 if (i2c_read(CFG_I2C_EEPROM_ADDR, INTEGRITY_SYSCFG_OFFSET,
189 CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
191 address = 0x800 + (int) value; /* Address of SYSCFG structure. */
193 /* Read NET CONFIG structure offset. */
194 if (i2c_read(CFG_I2C_EEPROM_ADDR, address,
195 CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
197 address = 0x800 + (int) value; /* Address of NET CONFIG structure. */
198 address += 12; /* Address of NET INTERFACE CONFIG structure. */
200 /* Read NET INTERFACE CONFIG 2 structure offset. */
201 if (i2c_read(CFG_I2C_EEPROM_ADDR, address,
202 CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
204 address = 0x800 + 16 + (int) value; /* Address of NET INTERFACE
205 * CONFIG 2 structure. */
207 /* Read MAC address. */
208 if (i2c_read(CFG_I2C_EEPROM_ADDR, address,
209 CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &mac[0], 8))
212 buf[0] = mac[0] >> 24;
213 buf[1] = mac[0] >> 16;
214 buf[2] = mac[0] >> 8;
216 buf[4] = mac[1] >> 24;
217 buf[5] = mac[1] >> 16;
222 printf("Read from EEPROM @ 0x%02x failed\n", CFG_I2C_EEPROM_ADDR);
226 /* Platform dependent initialisation. */
227 int misc_init_r(void)
231 u_int8_t env_enetaddr[6], eeprom_enetaddr[6];
232 char *tmp = getenv("ethaddr");
236 /* EMIF-A CS3 configuration for FPGA. */
237 REG(DAVINCI_A3CR) = DAVINCI_A3CR_VAL;
239 clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1);
241 printf("ARM Clock: %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27) / 2);
242 printf("DDR Clock: %dMHz\n", (clk / 2));
244 /* Configure I2C switch (PCA9543) to enable channel 0. */
245 i2cbuf = CFG_I2C_PCA9543_ENABLE_CH0;
246 if (i2c_write(CFG_I2C_PCA9543_ADDR, 0,
247 CFG_I2C_PCA9543_ADDR_LEN, &i2cbuf, 1)) {
248 printf("Write to MUX @ 0x%02x failed\n", CFG_I2C_PCA9543_ADDR);
252 /* Read Ethernet MAC address from the U-Boot environment. */
253 for (i = 0; i < 6; i++) {
254 env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
256 tmp = (*end) ? end+1 : end;
259 /* Read Ethernet MAC address from EEPROM. */
260 if (read_mac_address(eeprom_enetaddr) == 0) {
261 if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6) != 0 &&
262 memcmp(env_enetaddr, eeprom_enetaddr, 6) != 0) {
263 printf("\nWarning: MAC addresses don't match:\n");
264 printf("\tHW MAC address: "
265 "%02X:%02X:%02X:%02X:%02X:%02X\n",
266 eeprom_enetaddr[0], eeprom_enetaddr[1],
267 eeprom_enetaddr[2], eeprom_enetaddr[3],
268 eeprom_enetaddr[4], eeprom_enetaddr[5]);
269 printf("\t\"ethaddr\" value: "
270 "%02X:%02X:%02X:%02X:%02X:%02X\n",
271 env_enetaddr[0], env_enetaddr[1],
272 env_enetaddr[2], env_enetaddr[3],
273 env_enetaddr[4], env_enetaddr[5]) ;
274 debug("### Set MAC addr from environment\n");
275 memcpy(eeprom_enetaddr, env_enetaddr, 6);
280 sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
281 eeprom_enetaddr[0], eeprom_enetaddr[1],
282 eeprom_enetaddr[2], eeprom_enetaddr[3],
283 eeprom_enetaddr[4], eeprom_enetaddr[5]) ;
284 debug("### Set environment from HW MAC addr = \"%s\"\n",
286 setenv("ethaddr", ethaddr);
291 printf("Ethernet init failed\n");
293 /* On this platform, U-Boot is copied in RAM by the UBL,
294 * so we are always in the relocated state. */
295 gd->flags |= GD_FLG_RELOC;
302 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
303 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;