2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4 * Based on da830evm.c. Original Copyrights follow:
6 * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 #include <asm/arch/hardware.h>
29 #include <asm/arch/emif_defs.h>
30 #include <asm/arch/emac_defs.h>
32 #include <asm/arch/davinci_misc.h>
35 DECLARE_GLOBAL_DATA_PTR;
37 #define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
39 /* SPI0 pin muxer settings */
40 static const struct pinmux_config spi1_pins[] = {
47 /* UART pin muxer settings */
48 static const struct pinmux_config uart_pins[] = {
55 #ifdef CONFIG_DRIVER_TI_EMAC
56 static const struct pinmux_config emac_pins[] = {
57 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
65 #else /* ! CONFIG_DRIVER_TI_EMAC_USE_RMII */
81 #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
86 /* I2C pin muxer settings */
87 static const struct pinmux_config i2c_pins[] = {
92 #ifdef CONFIG_NAND_DAVINCI
93 const struct pinmux_config nand_pins[] = {
106 { pinmux(12), 1, 5 },
109 #elif defined(CONFIG_USE_NOR)
110 /* NOR pin muxer settings */
111 const struct pinmux_config nor_pins[] = {
112 /* GP0[11] is required for NOR to work on Rev 3 EVMs */
113 { pinmux(0), 8, 4 }, /* GP0[11] */
135 { pinmux(10), 1, 0 },
136 { pinmux(10), 1, 1 },
137 { pinmux(10), 1, 2 },
138 { pinmux(10), 1, 3 },
139 { pinmux(10), 1, 4 },
140 { pinmux(10), 1, 5 },
141 { pinmux(10), 1, 6 },
142 { pinmux(10), 1, 7 },
143 { pinmux(11), 1, 0 },
144 { pinmux(11), 1, 1 },
145 { pinmux(11), 1, 2 },
146 { pinmux(11), 1, 3 },
147 { pinmux(11), 1, 4 },
148 { pinmux(11), 1, 5 },
149 { pinmux(11), 1, 6 },
150 { pinmux(11), 1, 7 },
151 { pinmux(12), 1, 0 },
152 { pinmux(12), 1, 1 },
153 { pinmux(12), 1, 2 },
154 { pinmux(12), 1, 3 },
155 { pinmux(12), 1, 4 },
156 { pinmux(12), 1, 5 },
157 { pinmux(12), 1, 6 },
162 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
167 #endif /* CONFIG_DRIVER_TI_EMAC */
169 void dsp_lpsc_on(unsigned domain, unsigned int id)
171 dv_reg_p mdstat, mdctl, ptstat, ptcmd;
172 struct davinci_psc_regs *psc_regs;
174 psc_regs = davinci_psc0_regs;
175 mdstat = &psc_regs->psc0.mdstat[id];
176 mdctl = &psc_regs->psc0.mdctl[id];
177 ptstat = &psc_regs->ptstat;
178 ptcmd = &psc_regs->ptcmd;
180 while (*ptstat & (0x1 << domain))
183 if ((*mdstat & 0x1f) == 0x03)
184 return; /* Already on and enabled */
188 *ptcmd = 0x1 << domain;
190 while (*ptstat & (0x1 << domain))
192 while ((*mdstat & 0x1f) != 0x03)
193 ; /* Probably an overkill... */
196 static void dspwake(void)
198 unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
201 /* if the device is ARM only, return */
202 if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10)
205 if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL))
208 *resetvect++ = 0x1E000; /* DSP Idle */
209 /* clear out the next 10 words as NOP */
210 memset(resetvect, 0, sizeof(unsigned) *10);
212 /* setup the DSP reset vector */
213 writel(DAVINCI_L3CBARAM_BASE, HOST1CFG);
215 dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
216 val = readl(PSC0_MDCTL + (15 * 4));
218 writel(val, (PSC0_MDCTL + (15 * 4)));
221 int misc_init_r(void)
227 static const struct pinmux_resource pinmuxes[] = {
228 #ifdef CONFIG_SPI_FLASH
229 PINMUX_ITEM(spi1_pins),
231 PINMUX_ITEM(uart_pins),
232 PINMUX_ITEM(i2c_pins),
233 #ifdef CONFIG_NAND_DAVINCI
234 PINMUX_ITEM(nand_pins),
235 #elif defined(CONFIG_USE_NOR)
236 PINMUX_ITEM(nor_pins),
240 static const struct lpsc_resource lpsc[] = {
241 { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
242 { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
243 { DAVINCI_LPSC_EMAC }, /* image download */
244 { DAVINCI_LPSC_UART2 }, /* console */
245 { DAVINCI_LPSC_GPIO },
248 #ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
249 #define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000
253 * get_board_rev() - setup to pass kernel board revision information
255 * bit[0-3] Maximum cpu clock rate supported by onboard SoC
261 u32 get_board_rev(void)
264 u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK;
267 s = getenv("maxcpuclk");
269 maxcpuclk = simple_strtoul(s, NULL, 10);
271 if (maxcpuclk >= 456000000)
273 else if (maxcpuclk >= 408000000)
275 else if (maxcpuclk >= 372000000)
281 int board_early_init_f(void)
284 * Power on required peripherals
285 * ARM does not have access by default to PSC0 and PSC1
286 * assuming here that the DSP bootloader has set the IOPU
287 * such that PSC access is available to ARM
289 if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
297 #ifdef CONFIG_USE_NOR
301 #ifndef CONFIG_USE_IRQ
305 #ifdef CONFIG_NAND_DAVINCI
307 * NAND CS setup - cycle counts based on da850evm NAND timings in the
308 * Linux kernel @ 25MHz EMIFA
310 writel((DAVINCI_ABCR_WSETUP(0) |
311 DAVINCI_ABCR_WSTROBE(1) |
312 DAVINCI_ABCR_WHOLD(0) |
313 DAVINCI_ABCR_RSETUP(0) |
314 DAVINCI_ABCR_RSTROBE(1) |
315 DAVINCI_ABCR_RHOLD(0) |
317 DAVINCI_ABCR_ASIZE_8BIT),
318 &davinci_emif_regs->ab2cr); /* CS3 */
321 /* arch number of the board */
322 gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
324 /* address of boot parameters */
325 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
327 /* setup the SUSPSRC for ARM to control emulation suspend */
328 writel(readl(&davinci_syscfg_regs->suspsrc) &
329 ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
330 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
331 DAVINCI_SYSCFG_SUSPSRC_UART2),
332 &davinci_syscfg_regs->suspsrc);
334 /* configure pinmux settings */
335 if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
338 #ifdef CONFIG_USE_NOR
339 /* Set the GPIO direction as output */
340 clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
342 /* Set the output as low */
343 val = readl(GPIO_BANK0_REG_SET_ADDR);
345 writel(val, GPIO_BANK0_REG_CLR_ADDR);
348 #ifdef CONFIG_DRIVER_TI_EMAC
349 if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
352 davinci_emac_mii_mode_sel(HAS_RMII);
353 #endif /* CONFIG_DRIVER_TI_EMAC */
355 /* enable the console UART */
356 writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
357 DAVINCI_UART_PWREMU_MGMT_UTRST),
358 &davinci_uart2_ctrl_regs->pwremu_mgmt);
363 #ifdef CONFIG_DRIVER_TI_EMAC
365 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
369 * DA850/OMAP-L138 EVM can interface to a daughter card for
370 * additional features. This card has an I2C GPIO Expander TCA6416
371 * to select the required functions like camera, RMII Ethernet,
372 * character LCD, video.
374 * Initialization of the expander involves configuring the
375 * polarity and direction of the ports. P07-P05 are used here.
376 * These ports are connected to a Mux chip which enables only one
377 * functionality at a time.
379 * For RMII phy to respond, the MII MDIO clock has to be disabled
380 * since both the PHY devices have address as zero. The MII MDIO
381 * clock is controlled via GPIO2[6].
383 * This code is valid for Beta version of the hardware
385 int rmii_hw_init(void)
387 const struct pinmux_config gpio_pins[] = {
394 /* PinMux for GPIO */
395 if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
398 /* I2C Exapnder configuration */
399 /* Set polarity to non-inverted */
402 ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2);
404 printf("\nExpander @ 0x%02x write FAILED!!!\n",
405 CONFIG_SYS_I2C_EXPANDER_ADDR);
409 /* Configure P07-P05 as outputs */
412 ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2);
414 printf("\nExpander @ 0x%02x write FAILED!!!\n",
415 CONFIG_SYS_I2C_EXPANDER_ADDR);
418 /* For Ethernet RMII selection
423 if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
424 printf("\nExpander @ 0x%02x read FAILED!!!\n",
425 CONFIG_SYS_I2C_EXPANDER_ADDR);
429 buf[0] |= (0 << 7) | (1 << 6) | (1 << 5);
430 if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
431 printf("\nExpander @ 0x%02x write FAILED!!!\n",
432 CONFIG_SYS_I2C_EXPANDER_ADDR);
435 /* Set the output as high */
436 temp = REG(GPIO_BANK2_REG_SET_ADDR);
438 REG(GPIO_BANK2_REG_SET_ADDR) = temp;
440 /* Set the GPIO direction as output */
441 temp = REG(GPIO_BANK2_REG_DIR_ADDR);
442 temp &= ~(0x01 << 6);
443 REG(GPIO_BANK2_REG_DIR_ADDR) = temp;
447 #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
450 * Initializes on-board ethernet controllers.
452 int board_eth_init(bd_t *bis)
454 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
455 /* Select RMII fucntion through the expander */
457 printf("RMII hardware init failed!!!\n");
459 if (!davinci_emac_initialize()) {
460 printf("Error: Ethernet init failed!\n");
466 #endif /* CONFIG_DRIVER_TI_EMAC */