2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4 * Based on da830evm.c. Original Copyrights follow:
6 * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 #include <asm/arch/hardware.h>
29 #include <asm/arch/emif_defs.h>
30 #include <asm/arch/emac_defs.h>
32 #include <asm/arch/davinci_misc.h>
35 DECLARE_GLOBAL_DATA_PTR;
37 /* SPI0 pin muxer settings */
38 static const struct pinmux_config spi1_pins[] = {
45 /* UART pin muxer settings */
46 static const struct pinmux_config uart_pins[] = {
53 #ifdef CONFIG_DRIVER_TI_EMAC
54 static const struct pinmux_config emac_pins[] = {
55 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
63 #else /* ! CONFIG_DRIVER_TI_EMAC_USE_RMII */
79 #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
84 /* I2C pin muxer settings */
85 static const struct pinmux_config i2c_pins[] = {
90 #ifdef CONFIG_NAND_DAVINCI
91 const struct pinmux_config nand_pins[] = {
104 { pinmux(12), 1, 5 },
107 #elif defined(CONFIG_USE_NOR)
108 /* NOR pin muxer settings */
109 const struct pinmux_config nor_pins[] = {
110 /* GP0[11] is required for NOR to work on Rev 3 EVMs */
111 { pinmux(0), 8, 4 }, /* GP0[11] */
133 { pinmux(10), 1, 0 },
134 { pinmux(10), 1, 1 },
135 { pinmux(10), 1, 2 },
136 { pinmux(10), 1, 3 },
137 { pinmux(10), 1, 4 },
138 { pinmux(10), 1, 5 },
139 { pinmux(10), 1, 6 },
140 { pinmux(10), 1, 7 },
141 { pinmux(11), 1, 0 },
142 { pinmux(11), 1, 1 },
143 { pinmux(11), 1, 2 },
144 { pinmux(11), 1, 3 },
145 { pinmux(11), 1, 4 },
146 { pinmux(11), 1, 5 },
147 { pinmux(11), 1, 6 },
148 { pinmux(11), 1, 7 },
149 { pinmux(12), 1, 0 },
150 { pinmux(12), 1, 1 },
151 { pinmux(12), 1, 2 },
152 { pinmux(12), 1, 3 },
153 { pinmux(12), 1, 4 },
154 { pinmux(12), 1, 5 },
155 { pinmux(12), 1, 6 },
160 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
165 #endif /* CONFIG_DRIVER_TI_EMAC */
167 void dsp_lpsc_on(unsigned domain, unsigned int id)
169 dv_reg_p mdstat, mdctl, ptstat, ptcmd;
170 struct davinci_psc_regs *psc_regs;
172 psc_regs = davinci_psc0_regs;
173 mdstat = &psc_regs->psc0.mdstat[id];
174 mdctl = &psc_regs->psc0.mdctl[id];
175 ptstat = &psc_regs->ptstat;
176 ptcmd = &psc_regs->ptcmd;
178 while (*ptstat & (0x1 << domain))
181 if ((*mdstat & 0x1f) == 0x03)
182 return; /* Already on and enabled */
186 *ptcmd = 0x1 << domain;
188 while (*ptstat & (0x1 << domain))
190 while ((*mdstat & 0x1f) != 0x03)
191 ; /* Probably an overkill... */
194 static void dspwake(void)
196 unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
199 /* if the device is ARM only, return */
200 if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10)
203 if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL))
206 *resetvect++ = 0x1E000; /* DSP Idle */
207 /* clear out the next 10 words as NOP */
208 memset(resetvect, 0, sizeof(unsigned) *10);
210 /* setup the DSP reset vector */
211 writel(DAVINCI_L3CBARAM_BASE, HOST1CFG);
213 dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
214 val = readl(PSC0_MDCTL + (15 * 4));
216 writel(val, (PSC0_MDCTL + (15 * 4)));
219 int misc_init_r(void)
225 static const struct pinmux_resource pinmuxes[] = {
226 #ifdef CONFIG_DRIVER_TI_EMAC
227 PINMUX_ITEM(emac_pins),
229 #ifdef CONFIG_SPI_FLASH
230 PINMUX_ITEM(spi1_pins),
232 PINMUX_ITEM(uart_pins),
233 PINMUX_ITEM(i2c_pins),
234 #ifdef CONFIG_NAND_DAVINCI
235 PINMUX_ITEM(nand_pins),
236 #elif defined(CONFIG_USE_NOR)
237 PINMUX_ITEM(nor_pins),
241 static const struct lpsc_resource lpsc[] = {
242 { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
243 { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
244 { DAVINCI_LPSC_EMAC }, /* image download */
245 { DAVINCI_LPSC_UART2 }, /* console */
246 { DAVINCI_LPSC_GPIO },
249 #ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
250 #define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000
254 * get_board_rev() - setup to pass kernel board revision information
256 * bit[0-3] Maximum cpu clock rate supported by onboard SoC
262 u32 get_board_rev(void)
265 u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK;
268 s = getenv("maxcpuclk");
270 maxcpuclk = simple_strtoul(s, NULL, 10);
272 if (maxcpuclk >= 456000000)
274 else if (maxcpuclk >= 408000000)
276 else if (maxcpuclk >= 372000000)
282 int board_early_init_f(void)
285 * Power on required peripherals
286 * ARM does not have access by default to PSC0 and PSC1
287 * assuming here that the DSP bootloader has set the IOPU
288 * such that PSC access is available to ARM
290 if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
298 #ifdef CONFIG_USE_NOR
302 #ifndef CONFIG_USE_IRQ
306 #ifdef CONFIG_NAND_DAVINCI
308 * NAND CS setup - cycle counts based on da850evm NAND timings in the
309 * Linux kernel @ 25MHz EMIFA
311 writel((DAVINCI_ABCR_WSETUP(0) |
312 DAVINCI_ABCR_WSTROBE(1) |
313 DAVINCI_ABCR_WHOLD(0) |
314 DAVINCI_ABCR_RSETUP(0) |
315 DAVINCI_ABCR_RSTROBE(1) |
316 DAVINCI_ABCR_RHOLD(0) |
318 DAVINCI_ABCR_ASIZE_8BIT),
319 &davinci_emif_regs->ab2cr); /* CS3 */
322 /* arch number of the board */
323 gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
325 /* address of boot parameters */
326 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
328 /* setup the SUSPSRC for ARM to control emulation suspend */
329 writel(readl(&davinci_syscfg_regs->suspsrc) &
330 ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
331 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
332 DAVINCI_SYSCFG_SUSPSRC_UART2),
333 &davinci_syscfg_regs->suspsrc);
335 /* configure pinmux settings */
336 if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
339 #ifdef CONFIG_USE_NOR
340 /* Set the GPIO direction as output */
341 clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
343 /* Set the output as low */
344 val = readl(GPIO_BANK0_REG_SET_ADDR);
346 writel(val, GPIO_BANK0_REG_CLR_ADDR);
349 #ifdef CONFIG_DRIVER_TI_EMAC
350 davinci_emac_mii_mode_sel(HAS_RMII);
351 #endif /* CONFIG_DRIVER_TI_EMAC */
353 /* enable the console UART */
354 writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
355 DAVINCI_UART_PWREMU_MGMT_UTRST),
356 &davinci_uart2_ctrl_regs->pwremu_mgmt);
361 #ifdef CONFIG_DRIVER_TI_EMAC
363 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
367 * DA850/OMAP-L138 EVM can interface to a daughter card for
368 * additional features. This card has an I2C GPIO Expander TCA6416
369 * to select the required functions like camera, RMII Ethernet,
370 * character LCD, video.
372 * Initialization of the expander involves configuring the
373 * polarity and direction of the ports. P07-P05 are used here.
374 * These ports are connected to a Mux chip which enables only one
375 * functionality at a time.
377 * For RMII phy to respond, the MII MDIO clock has to be disabled
378 * since both the PHY devices have address as zero. The MII MDIO
379 * clock is controlled via GPIO2[6].
381 * This code is valid for Beta version of the hardware
383 int rmii_hw_init(void)
385 const struct pinmux_config gpio_pins[] = {
392 /* PinMux for GPIO */
393 if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
396 /* I2C Exapnder configuration */
397 /* Set polarity to non-inverted */
400 ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2);
402 printf("\nExpander @ 0x%02x write FAILED!!!\n",
403 CONFIG_SYS_I2C_EXPANDER_ADDR);
407 /* Configure P07-P05 as outputs */
410 ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2);
412 printf("\nExpander @ 0x%02x write FAILED!!!\n",
413 CONFIG_SYS_I2C_EXPANDER_ADDR);
416 /* For Ethernet RMII selection
421 if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
422 printf("\nExpander @ 0x%02x read FAILED!!!\n",
423 CONFIG_SYS_I2C_EXPANDER_ADDR);
427 buf[0] |= (0 << 7) | (1 << 6) | (1 << 5);
428 if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
429 printf("\nExpander @ 0x%02x write FAILED!!!\n",
430 CONFIG_SYS_I2C_EXPANDER_ADDR);
433 /* Set the output as high */
434 temp = REG(GPIO_BANK2_REG_SET_ADDR);
436 REG(GPIO_BANK2_REG_SET_ADDR) = temp;
438 /* Set the GPIO direction as output */
439 temp = REG(GPIO_BANK2_REG_DIR_ADDR);
440 temp &= ~(0x01 << 6);
441 REG(GPIO_BANK2_REG_DIR_ADDR) = temp;
445 #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
448 * Initializes on-board ethernet controllers.
450 int board_eth_init(bd_t *bis)
452 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
453 /* Select RMII fucntion through the expander */
455 printf("RMII hardware init failed!!!\n");
457 if (!davinci_emac_initialize()) {
458 printf("Error: Ethernet init failed!\n");
464 #endif /* CONFIG_DRIVER_TI_EMAC */