3 * (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/mx31.h>
27 #include <asm/arch/mx31-regs.h>
31 #include "qong_fpga.h"
33 DECLARE_GLOBAL_DATA_PTR;
37 /* dram_init must store complete ramsize in gd->ram_size */
38 gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
43 static void qong_fpga_reset(void)
45 mxc_gpio_set(QONG_FPGA_RST_PIN, 0);
47 mxc_gpio_set(QONG_FPGA_RST_PIN, 1);
52 int board_early_init_f (void)
54 #ifdef CONFIG_QONG_FPGA
55 /* CS1: FPGA/Network Controller/GPIO */
56 /* 16-bit, no DTACK */
57 __REG(CSCR_U(1)) = 0x00000A01;
58 __REG(CSCR_L(1)) = 0x20040501;
59 __REG(CSCR_A(1)) = 0x04020C00;
61 /* setup pins for FPGA */
62 mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO));
63 mx31_gpio_mux(IOMUX_MODE(0x7e, MUX_CTL_GPIO));
64 mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO));
65 mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO));
66 mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO));
70 mxc_gpio_set(QONG_FPGA_RST_PIN, 0);
71 mxc_gpio_direction(QONG_FPGA_RST_PIN, MXC_GPIO_DIRECTION_OUT);
73 /* set interrupt pin as input */
74 mxc_gpio_direction(QONG_FPGA_IRQ_PIN, MXC_GPIO_DIRECTION_IN);
78 /* setup pins for UART1 */
79 mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
80 mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
81 mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
82 mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
84 /* setup pins for SPI (pmic) */
85 mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
86 mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
87 mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
88 mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
89 mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
98 /* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */
99 /* Assumptions: HCLK = 133 MHz, tACC = 130ns */
100 __REG(CSCR_U(0)) = ((0 << 31) | /* SP */
102 (0 << 28) | /* BCD */
103 (0 << 24) | /* BCS */
104 (0 << 22) | /* PSZ */
105 (0 << 21) | /* PME */
106 (0 << 20) | /* SYNC */
107 (0 << 16) | /* DOL */
108 (3 << 14) | /* CNC */
109 (21 << 8) | /* WSC */
115 __REG(CSCR_L(0)) = ((2 << 28) | /* OEA */
116 (1 << 24) | /* OEN */
117 (3 << 20) | /* EBWA */
118 (3 << 16) | /* EBWN */
119 (1 << 12) | /* CSA */
120 (1 << 11) | /* EBC */
125 (0 << 1) | /* WRAP */
129 __REG(CSCR_A(0)) = ((2 << 28) | /* EBRA */
130 (1 << 24) | /* EBRN */
131 (2 << 20) | /* RWA */
132 (2 << 16) | /* RWN */
133 (0 << 15) | /* MUM */
134 (0 << 13) | /* LAH */
135 (2 << 10) | /* LBN */
141 (0 << 1) | /* CNC2 */
145 /* board id for linux */
146 gd->bd->bi_arch_number = MACH_TYPE_QONG;
147 gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
152 int board_late_init(void)
156 /* Enable RTC battery */
157 val = pmic_reg_read(REG_POWER_CTL0);
158 pmic_reg_write(REG_POWER_CTL0, val | COINCHEN);
159 pmic_reg_write(REG_INT_STATUS1, RTCRSTI);
164 int checkboard (void)
166 printf("Board: DAVE/DENX Qong\n");
170 int misc_init_r (void)
172 #ifdef CONFIG_QONG_FPGA
175 tmp = *(volatile u32*)QONG_FPGA_CTRL_VERSION;
177 printf("version register = %u.%u.%u\n",
178 (tmp & 0xF000) >> 12, (tmp & 0x0F00) >> 8, tmp & 0x00FF);
183 int board_eth_init(bd_t *bis)
185 #if defined(CONFIG_QONG_FPGA) && defined(CONFIG_DNET)
186 return dnet_eth_initialize(0, (void *)CONFIG_DNET_BASE, -1);
192 #if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT)
193 static void board_nand_setup(void)
196 /* CS3: NAND 8-bit */
197 __REG(CSCR_U(3)) = 0x00004f00;
198 __REG(CSCR_L(3)) = 0x20013b31;
199 __REG(CSCR_A(3)) = 0x00020800;
200 __REG(IOMUXC_GPR) |= 1 << 13;
202 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO));
203 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO));
204 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_RB, MUX_CTL_IN_GPIO));
206 /* Make sure to reset the fpga else you cannot access NAND */
209 /* Enable NAND flash */
212 mxc_gpio_direction(15, MXC_GPIO_DIRECTION_OUT);
213 mxc_gpio_direction(16, MXC_GPIO_DIRECTION_IN);
214 mxc_gpio_direction(14, MXC_GPIO_DIRECTION_IN);
219 int qong_nand_rdy(void *chip)
222 return mxc_gpio_get(16);
225 void qong_nand_select_chip(struct mtd_info *mtd, int chip)
234 void qong_nand_plat_init(void *chip)
236 struct nand_chip *nand = (struct nand_chip *)chip;
237 nand->chip_delay = 20;
238 nand->select_chip = qong_nand_select_chip;
239 nand->options &= ~NAND_BUSWIDTH_16;