3 * (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/mx31.h>
27 #include <asm/arch/mx31-regs.h>
28 #include "qong_fpga.h"
30 DECLARE_GLOBAL_DATA_PTR;
34 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
35 gd->bd->bi_dram[0].size = get_ram_size((volatile void *)PHYS_SDRAM_1,
44 /* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */
45 /* Assumptions: HCLK = 133 MHz, tACC = 130ns */
46 __REG(CSCR_U(0)) = ((0 << 31) | /* SP */
52 (0 << 20) | /* SYNC */
61 __REG(CSCR_L(0)) = ((2 << 28) | /* OEA */
63 (3 << 20) | /* EBWA */
64 (3 << 16) | /* EBWN */
75 __REG(CSCR_A(0)) = ((2 << 28) | /* EBRA */
76 (1 << 24) | /* EBRN */
91 #ifdef CONFIG_QONG_FPGA
92 /* CS1: FPGA/Network Controller/GPIO */
93 /* 16-bit, no DTACK */
94 __REG(CSCR_U(1)) = 0x00000A01;
95 __REG(CSCR_L(1)) = 0x20040501;
96 __REG(CSCR_A(1)) = 0x04020C00;
98 /* setup pins for FPGA */
99 mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO));
100 mx31_gpio_mux(IOMUX_MODE(0x7e, MUX_CTL_GPIO));
101 mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO));
102 mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO));
103 mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO));
106 /* setup pins for UART1 */
107 mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
108 mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
109 mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
110 mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
112 /* board id for linux */
113 gd->bd->bi_arch_number = MACH_TYPE_QONG;
114 gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
119 int checkboard (void)
121 printf("Board: DAVE/DENX QongEVB-LITE\n");
125 int misc_init_r (void)
127 #ifdef CONFIG_QONG_FPGA
132 tmp = __REG(GPIO2_BASE + GPIO_DR);
133 tmp &= (~(1 << QONG_FPGA_RST_PIN));
134 __REG(GPIO2_BASE + GPIO_DR) = tmp;
135 /* set the GPIO as output */
136 tmp = __REG(GPIO2_BASE + GPIO_GDIR);
137 tmp |= (1 << QONG_FPGA_RST_PIN);
138 __REG(GPIO2_BASE + GPIO_GDIR) = tmp;
142 tmp = __REG(GPIO2_BASE + GPIO_DR);
143 tmp |= (1 << QONG_FPGA_RST_PIN);
144 __REG(GPIO2_BASE + GPIO_DR) = tmp;
145 /* set interrupt pin as input */
146 __REG(GPIO2_BASE + GPIO_GDIR) = tmp | (1 << QONG_FPGA_IRQ_PIN);
147 /* wait while the FPGA starts */
150 tmp = *(volatile u32*)QONG_FPGA_CTRL_VERSION;
152 printf("version register = %u.%u.%u\n",
153 (tmp & 0xF000) >> 12, (tmp & 0x0F00) >> 8, tmp & 0x00FF);
159 int board_eth_init(bd_t *bis)
161 #if defined(CONFIG_QONG_FPGA) && defined(CONFIG_DNET)
162 return dnet_eth_initialize(0, (void *)CONFIG_DNET_BASE, -1);