3 * (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/clock.h>
27 #include <asm/arch/imx-regs.h>
32 #include "qong_fpga.h"
35 DECLARE_GLOBAL_DATA_PTR;
37 #ifdef CONFIG_HW_WATCHDOG
38 void hw_watchdog_reset(void)
40 mxc_hw_watchdog_reset();
46 /* dram_init must store complete ramsize in gd->ram_size */
47 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
52 static void qong_fpga_reset(void)
54 gpio_set_value(QONG_FPGA_RST_PIN, 0);
56 gpio_set_value(QONG_FPGA_RST_PIN, 1);
61 int board_early_init_f (void)
63 #ifdef CONFIG_QONG_FPGA
64 /* CS1: FPGA/Network Controller/GPIO */
65 /* 16-bit, no DTACK */
66 __REG(CSCR_U(1)) = 0x00000A01;
67 __REG(CSCR_L(1)) = 0x20040501;
68 __REG(CSCR_A(1)) = 0x04020C00;
70 /* setup pins for FPGA */
71 mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO));
72 mx31_gpio_mux(IOMUX_MODE(0x7e, MUX_CTL_GPIO));
73 mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO));
74 mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO));
75 mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO));
79 gpio_direction_output(QONG_FPGA_RST_PIN, 0);
81 /* set interrupt pin as input */
82 gpio_direction_input(QONG_FPGA_IRQ_PIN);
84 /* FPGA JTAG Interface */
85 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS6, MUX_CTL_GPIO));
86 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK6, MUX_CTL_GPIO));
87 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CAPTURE, MUX_CTL_GPIO));
88 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_COMPARE, MUX_CTL_GPIO));
89 gpio_direction_output(QONG_FPGA_TCK_PIN, 0);
90 gpio_direction_output(QONG_FPGA_TMS_PIN, 0);
91 gpio_direction_output(QONG_FPGA_TDI_PIN, 0);
92 gpio_direction_input(QONG_FPGA_TDO_PIN);
95 /* setup pins for UART1 */
96 mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
97 mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
98 mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
99 mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
101 /* setup pins for SPI (pmic) */
102 mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
103 mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
104 mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
105 mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
106 mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
108 /* Setup pins for USB2 Host */
109 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_CLK, MUX_CTL_FUNC));
110 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DIR, MUX_CTL_FUNC));
111 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_NXT, MUX_CTL_FUNC));
112 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC));
113 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC));
114 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC));
115 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD3, MUX_CTL_FUNC));
116 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD3, MUX_CTL_FUNC));
117 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK3, MUX_CTL_FUNC));
118 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS3, MUX_CTL_FUNC));
119 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD6, MUX_CTL_FUNC));
120 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD6, MUX_CTL_FUNC));
122 #define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
123 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
125 mx31_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
126 mx31_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
127 mx31_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
128 mx31_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
129 mx31_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
130 mx31_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
131 mx31_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
132 mx31_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
133 mx31_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
134 mx31_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
135 mx31_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
136 mx31_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
138 writel(readl((IOMUXC_BASE + 0x8)) | (1 << 11), IOMUXC_BASE + 0x8);
144 int board_init (void)
147 /* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */
148 /* Assumptions: HCLK = 133 MHz, tACC = 130ns */
149 __REG(CSCR_U(0)) = ((0 << 31) | /* SP */
151 (0 << 28) | /* BCD */
152 (0 << 24) | /* BCS */
153 (0 << 22) | /* PSZ */
154 (0 << 21) | /* PME */
155 (0 << 20) | /* SYNC */
156 (0 << 16) | /* DOL */
157 (3 << 14) | /* CNC */
158 (21 << 8) | /* WSC */
164 __REG(CSCR_L(0)) = ((2 << 28) | /* OEA */
165 (1 << 24) | /* OEN */
166 (3 << 20) | /* EBWA */
167 (3 << 16) | /* EBWN */
168 (1 << 12) | /* CSA */
169 (1 << 11) | /* EBC */
174 (0 << 1) | /* WRAP */
178 __REG(CSCR_A(0)) = ((2 << 28) | /* EBRA */
179 (1 << 24) | /* EBRN */
180 (2 << 20) | /* RWA */
181 (2 << 16) | /* RWN */
182 (0 << 15) | /* MUM */
183 (0 << 13) | /* LAH */
184 (2 << 10) | /* LBN */
190 (0 << 1) | /* CNC2 */
194 /* board id for linux */
195 gd->bd->bi_arch_number = MACH_TYPE_QONG;
196 gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
203 int board_late_init(void)
207 /* Enable RTC battery */
208 val = pmic_reg_read(REG_POWER_CTL0);
209 pmic_reg_write(REG_POWER_CTL0, val | COINCHEN);
210 pmic_reg_write(REG_INT_STATUS1, RTCRSTI);
212 #ifdef CONFIG_HW_WATCHDOG
213 mxc_hw_watchdog_enable();
219 int checkboard (void)
221 printf("Board: DAVE/DENX Qong\n");
225 int misc_init_r (void)
227 #ifdef CONFIG_QONG_FPGA
230 tmp = *(volatile u32*)QONG_FPGA_CTRL_VERSION;
232 printf("version register = %u.%u.%u\n",
233 (tmp & 0xF000) >> 12, (tmp & 0x0F00) >> 8, tmp & 0x00FF);
238 int board_eth_init(bd_t *bis)
240 #if defined(CONFIG_QONG_FPGA) && defined(CONFIG_DNET)
241 return dnet_eth_initialize(0, (void *)CONFIG_DNET_BASE, -1);
247 #if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT)
248 static void board_nand_setup(void)
251 /* CS3: NAND 8-bit */
252 __REG(CSCR_U(3)) = 0x00004f00;
253 __REG(CSCR_L(3)) = 0x20013b31;
254 __REG(CSCR_A(3)) = 0x00020800;
255 __REG(IOMUXC_GPR) |= 1 << 13;
257 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO));
258 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO));
259 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_RB, MUX_CTL_IN_GPIO));
261 /* Make sure to reset the fpga else you cannot access NAND */
264 /* Enable NAND flash */
265 gpio_set_value(15, 1);
266 gpio_set_value(14, 1);
267 gpio_direction_output(15, 0);
268 gpio_direction_input(16);
269 gpio_direction_input(14);
273 int qong_nand_rdy(void *chip)
276 return gpio_get_value(16);
279 void qong_nand_select_chip(struct mtd_info *mtd, int chip)
282 gpio_set_value(15, 0);
284 gpio_set_value(15, 1);
288 void qong_nand_plat_init(void *chip)
290 struct nand_chip *nand = (struct nand_chip *)chip;
291 nand->chip_delay = 20;
292 nand->select_chip = qong_nand_select_chip;
293 nand->options &= ~NAND_BUSWIDTH_16;