3 * (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/mx31.h>
27 #include <asm/arch/mx31-regs.h>
30 #include "qong_fpga.h"
32 DECLARE_GLOBAL_DATA_PTR;
36 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
37 gd->bd->bi_dram[0].size = get_ram_size((volatile void *)PHYS_SDRAM_1,
43 static void qong_fpga_reset(void)
45 mx31_gpio_set(QONG_FPGA_RST_PIN, 0);
47 mx31_gpio_set(QONG_FPGA_RST_PIN, 1);
55 /* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */
56 /* Assumptions: HCLK = 133 MHz, tACC = 130ns */
57 __REG(CSCR_U(0)) = ((0 << 31) | /* SP */
63 (0 << 20) | /* SYNC */
72 __REG(CSCR_L(0)) = ((2 << 28) | /* OEA */
74 (3 << 20) | /* EBWA */
75 (3 << 16) | /* EBWN */
86 __REG(CSCR_A(0)) = ((2 << 28) | /* EBRA */
87 (1 << 24) | /* EBRN */
102 #ifdef CONFIG_QONG_FPGA
103 /* CS1: FPGA/Network Controller/GPIO */
104 /* 16-bit, no DTACK */
105 __REG(CSCR_U(1)) = 0x00000A01;
106 __REG(CSCR_L(1)) = 0x20040501;
107 __REG(CSCR_A(1)) = 0x04020C00;
109 /* setup pins for FPGA */
110 mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO));
111 mx31_gpio_mux(IOMUX_MODE(0x7e, MUX_CTL_GPIO));
112 mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO));
113 mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO));
114 mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO));
118 mx31_gpio_set(QONG_FPGA_RST_PIN, 0);
119 mx31_gpio_direction(QONG_FPGA_RST_PIN, MX31_GPIO_DIRECTION_OUT);
121 /* set interrupt pin as input */
122 mx31_gpio_direction(QONG_FPGA_IRQ_PIN, MX31_GPIO_DIRECTION_IN);
126 /* setup pins for UART1 */
127 mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
128 mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
129 mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
130 mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
132 /* setup pins for SPI (pmic) */
133 mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
134 mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
135 mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
136 mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
137 mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
139 /* board id for linux */
140 gd->bd->bi_arch_number = MACH_TYPE_QONG;
141 gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
146 int board_late_init(void)
150 /* Enable RTC battery */
151 val = pmic_reg_read(REG_POWER_CTL0);
152 pmic_reg_write(REG_POWER_CTL0, val | COINCHEN);
153 pmic_reg_write(REG_INT_STATUS1, RTCRSTI);
158 int checkboard (void)
160 printf("Board: DAVE/DENX Qong\n");
164 int misc_init_r (void)
166 #ifdef CONFIG_QONG_FPGA
169 tmp = *(volatile u32*)QONG_FPGA_CTRL_VERSION;
171 printf("version register = %u.%u.%u\n",
172 (tmp & 0xF000) >> 12, (tmp & 0x0F00) >> 8, tmp & 0x00FF);
177 int board_eth_init(bd_t *bis)
179 #if defined(CONFIG_QONG_FPGA) && defined(CONFIG_DNET)
180 return dnet_eth_initialize(0, (void *)CONFIG_DNET_BASE, -1);
186 #if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT)
187 static void board_nand_setup(void)
190 /* CS3: NAND 8-bit */
191 __REG(CSCR_U(3)) = 0x00004f00;
192 __REG(CSCR_L(3)) = 0x20013b31;
193 __REG(CSCR_A(3)) = 0x00020800;
194 __REG(IOMUXC_GPR) |= 1 << 13;
196 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO));
197 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO));
198 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_RB, MUX_CTL_IN_GPIO));
200 /* Make sure to reset the fpga else you cannot access NAND */
203 /* Enable NAND flash */
204 mx31_gpio_set(15, 1);
205 mx31_gpio_set(14, 1);
206 mx31_gpio_direction(15, MX31_GPIO_DIRECTION_OUT);
207 mx31_gpio_direction(16, MX31_GPIO_DIRECTION_IN);
208 mx31_gpio_direction(14, MX31_GPIO_DIRECTION_IN);
209 mx31_gpio_set(15, 0);
213 int qong_nand_rdy(void *chip)
216 return mx31_gpio_get(16);
219 void qong_nand_select_chip(struct mtd_info *mtd, int chip)
222 mx31_gpio_set(15, 0);
224 mx31_gpio_set(15, 1);
228 void qong_nand_plat_init(void *chip)
230 struct nand_chip *nand = (struct nand_chip *)chip;
231 nand->chip_delay = 20;
232 nand->select_chip = qong_nand_select_chip;
233 nand->options &= ~NAND_BUSWIDTH_16;