2 * Copyright (C) 2009, Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
4 * Based on board/freescale/mx31ads/lowlevel_init.S
5 * by Guennadi Liakhovetski.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <asm/arch/imx-regs.h>
45 .macro SETUP_RAM cfg, ctl
46 /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
47 REG 0xB8001010, 0x00000004
51 REG 0xB8001000, 0x92100000
52 REG 0x80000f00, 0x12344321
53 REG 0xB8001000, 0xa2100000
54 REG 0x80000000, 0x12344321
55 REG 0x80000000, 0x12344321
56 REG 0xB8001000, 0xb2100000
62 REG 0x80000000, 0xDEADBEEF
63 REG 0xB8001010, 0x0000000c
66 /* RedBoot: To support 133MHz DDR */
67 .macro init_drive_strength
69 * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
70 * in SW_PAD_CTL registers
74 ldr r1, =IOMUXC_SW_PAD_CTL(0x2b)
76 bic r0, r0, #(1 << 12)
81 bic r0, r0, #(1 << 22)
91 bic r0, r0, #(1 << 22)
96 bic r0, r0, #(1 << 22)
99 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
100 ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */
103 bic r0, r0, #(1 << 22)
104 bic r0, r0, #(1 << 12)
105 bic r0, r0, #(1 << 2)
110 .endm /* init_drive_strength */
117 /* Image Processing Unit: */
118 /* Too early to switch display on? */
119 /* Switch on Display Interface */
120 REG IPU_CONF, IPU_CONF_DI_EN
121 /* Clock Control Module: */
122 REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */
126 REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */
127 /* Switch to MCU PLL */
128 REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
135 ldr r1, MPCTL_PARAM_399
139 /* Set UPLL=240MHz, USB=60MHz */
143 ldr r1, UPCTL_PARAM_240
146 /* default CLKO to 1/8 of the ARM core */
151 /* Default: 1, 4, 12, 1 */
152 REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
155 /* Set stackpointer in internal RAM to call get_ram_size */
156 ldr sp, =(IRAM_BASE_ADDR + IRAM_SIZE - 16)
157 stmfd sp!, {r0-r11, ip, lr}
158 mov ip, lr /* save link reg across call */
161 SETUP_RAM ESDCFG0_256MB, ESDCTL0_256MB
168 SETUP_RAM ESDCFG0_128MB, ESDCTL0_128MB
177 ldmfd sp!, {r0-r11, ip, lr}
178 mov lr, ip /* restore link reg */
184 .word (((1 - 1) << 26) + ((52 - 1) << 16) + (7 << 10) + (35 << 0))
186 .word (((2 - 1) << 26) + ((13 - 1) << 16) + (9 << 10) + (3 << 0))
188 .equ ESDCFG0_128MB, \
189 (0 << 21) + /* tXP */ \
190 (1 << 20) + /* tWTR */ \
191 (2 << 18) + /* tRP */ \
192 (1 << 16) + /* tMRD */ \
193 (0 << 15) + /* tWR */ \
194 (5 << 12) + /* tRAS */ \
195 (1 << 10) + /* tRRD */ \
196 (3 << 8) + /* tCAS */ \
197 (2 << 4) + /* tRCD */ \
198 (0x0F << 0) /* tRC */
200 .equ ESDCTL0_128MB, \
201 (1 << 31) + /* enable */ \
202 (0 << 28) + /* mode */ \
203 (0 << 27) + /* supervisor protect */ \
204 (2 << 24) + /* 13 rows */ \
205 (2 << 20) + /* 10 cols */ \
206 (2 << 16) + /* 32 bit */ \
207 (3 << 13) + /* 7.81us (64ms/8192) */ \
208 (0 << 10) + /* power down timer */ \
209 (0 << 8) + /* full page */ \
210 (1 << 7) + /* burst length */ \
211 (0 << 0) /* precharge timer */
213 .equ ESDCFG0_256MB, \
214 (3 << 21) + /* tXP */ \
215 (0 << 20) + /* tWTR */ \
216 (2 << 18) + /* tRP */ \
217 (1 << 16) + /* tMRD */ \
218 (0 << 15) + /* tWR */ \
219 (5 << 12) + /* tRAS */ \
220 (1 << 10) + /* tRRD */ \
221 (3 << 8) + /* tCAS */ \
222 (2 << 4) + /* tRCD */ \
225 .equ ESDCTL0_256MB, \
229 (3 << 24) + /* 14 rows */ \
230 (2 << 20) + /* 10 cols */ \
232 (4 << 13) + /* 3.91us (64ms/16384) */ \