1 // SPDX-License-Identifier: GPL-2.0+
4 * Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
6 * Based on Kirkwood support:
8 * Marvell Semiconductor <www.marvell.com>
9 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/soc.h>
20 #include <asm/arch/mpp.h>
21 #include <asm/arch/gpio.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 int board_early_init_f(void)
28 /* Gpio configuration */
29 mvebu_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH,
30 DNS325_OE_LOW, DNS325_OE_HIGH);
32 /* Multi-Purpose Pins Functionality configuration */
33 static const u32 kwmpp_config[] = {
54 MPP20_SATA1_ACTn, /* sata1(left) status led */
55 MPP21_SATA0_ACTn, /* sata0(right) status led */
58 MPP24_GPIO, /* power off out */
60 MPP26_GPIO, /* power led */
61 MPP27_GPIO, /* sata0(right) error led */
62 MPP28_GPIO, /* sata1(left) error led */
63 MPP29_GPIO, /* usb error led */
68 MPP34_GPIO, /* power key */
73 MPP39_GPIO, /* enable sata 0 */
74 MPP40_GPIO, /* enable sata 1 */
75 MPP41_GPIO, /* hdd0 present */
76 MPP42_GPIO, /* hdd1 present */
77 MPP43_GPIO, /* usb status led */
78 MPP44_GPIO, /* fan status */
79 MPP45_GPIO, /* fan high speed */
80 MPP46_GPIO, /* fan low speed */
81 MPP47_GPIO, /* usb umount */
82 MPP48_GPIO, /* factory reset */
83 MPP49_GPIO, /* thermal sensor */
86 kirkwood_mpp_conf(kwmpp_config, NULL);
88 kw_gpio_set_blink(DNS325_GPIO_LED_POWER , 1);
90 kw_gpio_set_value(DNS325_GPIO_SATA0_EN , 1);
96 /* Boot parameters address */
97 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
102 #ifdef CONFIG_RESET_PHY_R
103 /* Configure and initialize PHY */
108 char *name = "egiga0";
110 if (miiphy_set_current_dev(name))
113 /* command to read PHY dev address */
114 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
115 printf("Err..(%s) could not read PHY dev address\n", __func__);
120 * Enable RGMII delay on Tx and Rx for CPU port
121 * Ref: sec 4.7.2 of chip datasheet
123 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
124 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
125 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
126 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
127 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
130 miiphy_reset(name, devadr);
132 debug("88E1116 Initialized on %s\n", name);
134 #endif /* CONFIG_RESET_PHY_R */