3 * Stefan Herbrechtsmeier <stefan@code.herbrechtsmeier.net>
5 * Based on Kirkwood support:
7 * Marvell Semiconductor <www.marvell.com>
8 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
32 #include <asm/arch/cpu.h>
33 #include <asm/arch/kirkwood.h>
34 #include <asm/arch/mpp.h>
35 #include <asm/arch/gpio.h>
38 DECLARE_GLOBAL_DATA_PTR;
40 int board_early_init_f(void)
42 /* Gpio configuration */
43 kw_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH,
44 DNS325_OE_LOW, DNS325_OE_HIGH);
46 /* Multi-Purpose Pins Functionality configuration */
47 u32 kwmpp_config[] = {
68 MPP20_SATA1_ACTn, /* sata1(left) status led */
69 MPP21_SATA0_ACTn, /* sata0(right) status led */
72 MPP24_GPIO, /* power off out */
74 MPP26_GPIO, /* power led */
75 MPP27_GPIO, /* sata0(right) error led */
76 MPP28_GPIO, /* sata1(left) error led */
77 MPP29_GPIO, /* usb error led */
82 MPP34_GPIO, /* power key */
87 MPP39_GPIO, /* enable sata 0 */
88 MPP40_GPIO, /* enable sata 1 */
89 MPP41_GPIO, /* hdd0 present */
90 MPP42_GPIO, /* hdd1 present */
91 MPP43_GPIO, /* usb status led */
92 MPP44_GPIO, /* fan status */
93 MPP45_GPIO, /* fan high speed */
94 MPP46_GPIO, /* fan low speed */
95 MPP47_GPIO, /* usb umount */
96 MPP48_GPIO, /* factory reset */
97 MPP49_GPIO, /* thermal sensor */
100 kirkwood_mpp_conf(kwmpp_config);
102 kw_gpio_set_blink(DNS325_GPIO_LED_POWER , 1);
104 kw_gpio_set_value(DNS325_GPIO_SATA0_EN , 1);
110 /* Boot parameters address */
111 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
116 #ifdef CONFIG_RESET_PHY_R
117 /* Configure and initialize PHY */
122 char *name = "egiga0";
124 if (miiphy_set_current_dev(name))
127 /* command to read PHY dev address */
128 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
129 printf("Err..(%s) could not read PHY dev address\n", __func__);
134 * Enable RGMII delay on Tx and Rx for CPU port
135 * Ref: sec 4.7.2 of chip datasheet
137 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
138 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
139 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
140 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
141 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
144 miiphy_reset(name, devadr);
146 debug("88E1116 Initialized on %s\n", name);
148 #endif /* CONFIG_RESET_PHY_R */