1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010-2017 CS Systemes d'Information
4 * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
5 * Christophe Leroy <christophe.leroy@c-s.fr>
13 #define BIT_CLE ((unsigned short)0x0800)
14 #define BIT_ALE ((unsigned short)0x0400)
15 #define BIT_NCE ((unsigned short)0x1000)
17 static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
19 struct nand_chip *this = mtd_to_nand(mtdinfo);
20 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
21 unsigned short pddat = 0;
23 /* The hardware control change */
24 if (ctrl & NAND_CTRL_CHANGE) {
25 pddat = in_be16(&immr->im_ioport.iop_pddat);
27 /* Clearing ALE and CLE */
28 pddat &= ~(BIT_CLE | BIT_ALE);
36 /* Driving CLE and ALE pin */
42 out_be16(&immr->im_ioport.iop_pddat, pddat);
45 /* Writing the command */
46 if (cmd != NAND_CMD_NONE)
47 out_8(this->IO_ADDR_W, cmd);
50 int board_nand_init(struct nand_chip *nand)
52 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
55 setbits_be16(&immr->im_ioport.iop_pddir, 0x1c00);
56 clrbits_be16(&immr->im_ioport.iop_pdpar, 0x1c00);
57 clrsetbits_be16(&immr->im_ioport.iop_pddat, 0x0c00, 0x1000);
59 nand->chip_delay = 60;
60 nand->ecc.mode = NAND_ECC_SOFT;
61 nand->cmd_ctrl = nand_hwcontrol;