2 * Copyright (C) 2010-2017 CS Systemes d'Information
3 * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
4 * Christophe Leroy <christophe.leroy@c-s.fr>
6 * SPDX-License-Identifier: GPL-2.0+
14 #define BIT_CLE ((unsigned short)0x0800)
15 #define BIT_ALE ((unsigned short)0x0400)
16 #define BIT_NCE ((unsigned short)0x1000)
18 static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
20 struct nand_chip *this = mtdinfo->priv;
21 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
22 unsigned short pddat = 0;
24 /* The hardware control change */
25 if (ctrl & NAND_CTRL_CHANGE) {
26 pddat = in_be16(&immr->im_ioport.iop_pddat);
28 /* Clearing ALE and CLE */
29 pddat &= ~(BIT_CLE | BIT_ALE);
37 /* Driving CLE and ALE pin */
43 out_be16(&immr->im_ioport.iop_pddat, pddat);
46 /* Writing the command */
47 if (cmd != NAND_CMD_NONE)
48 out_8(this->IO_ADDR_W, cmd);
51 int board_nand_init(struct nand_chip *nand)
53 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
56 setbits_be16(&immr->im_ioport.iop_pddir, 0x1c00);
57 clrbits_be16(&immr->im_ioport.iop_pdpar, 0x1c00);
58 clrsetbits_be16(&immr->im_ioport.iop_pddat, 0x0c00, 0x1000);
60 nand->chip_delay = 60;
61 nand->ecc.mode = NAND_ECC_SOFT;
62 nand->cmd_ctrl = nand_hwcontrol;