board/cssi/MCR3000/MCR3000.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2017 CS Systemes d'Information
   4  * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
   5  * Christophe Leroy <christophe.leroy@c-s.fr>
   6  *
   7  * Board specific routines for the MCR3000 board
   8  */
   9
  10 #include <common.h>
  11 #include <env.h>
  12 #include <hwconfig.h>
  13 #include <mpc8xx.h>
  14 #include <fdt_support.h>
  15 #include <serial.h>
  16 #include <asm/io.h>
  17 #include <dm/uclass.h>
  18 #include <wdt.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 #define SDRAM_MAX_SIZE                  (32 * 1024 * 1024)
  23
  24 static const uint cs1_dram_table_66[] = {
  25         /* DRAM - single read. (offset 0 in upm RAM) */
  26         0x0F3DFC04, 0x0FEFBC04, 0x00BE7804, 0x0FFDF400,
  27         0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  28
  29         /* DRAM - burst read. (offset 8 in upm RAM) */
  30         0x0F3DFC04, 0x0FEFBC04, 0x00BF7C04, 0x00FFFC00,
  31         0x00FFFC00, 0x00FEF800, 0x0FFDF400, 0x1FFFFC05,
  32         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  33         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  34
  35         /* DRAM - single write. (offset 18 in upm RAM) */
  36         0x0F3DFC04, 0x0FEFB800, 0x00BF7404, 0x0FFEF804,
  37         0x0FFDF404, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
  38
  39         /* DRAM - burst write. (offset 20 in upm RAM) */
  40         0x0F3DFC04, 0x0FEFB800, 0x00BF7400, 0x00FFFC00,
  41         0x00FFFC00, 0x00FFFC04, 0x0FFEF804, 0x0FFDF404,
  42         0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  43         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  44
  45         /* refresh  (offset 30 in upm RAM) */
  46         0x0FFDF404, 0x0FFEBC04, 0x0FFD7C84, 0x0FFFFC04,
  47         0x0FFFFC04, 0x0FFFFC04, 0x1FFFFC85, 0xFFFFFFFF,
  48
  49         /* init */
  50         0x0FEEB874, 0x0FBD7474, 0x1FFFFC45, 0xFFFFFFFF,
  51
  52         /* exception. (offset 3c in upm RAM) */
  53         0xFFFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  54 };
  55
  56 int ft_board_setup(void *blob, bd_t *bd)
  57 {
  58         const char *sync = "receive";
  59
  60         ft_cpu_setup(blob, bd);
  61
  62         /* BRG */
  63         do_fixup_by_path_u32(blob, "/soc/cpm", "brg-frequency",
  64                              bd->bi_busfreq, 1);
  65
  66         /* MAC addr */
  67         fdt_fixup_ethernet(blob);
  68
  69         /* Bus Frequency for CPM */
  70         do_fixup_by_path_u32(blob, "/soc", "bus-frequency", bd->bi_busfreq, 1);
  71
  72         /* E1 interface - Set data rate */
  73         do_fixup_by_path_u32(blob, "/localbus/e1-wan", "data-rate", 2, 1);
  74
  75         /* E1 interface - Set channel phase to 0 */
  76         do_fixup_by_path_u32(blob, "/localbus/e1-wan", "channel-phase", 0, 1);
  77
  78         /* E1 interface - rising edge sync pulse transmit */
  79         do_fixup_by_path(blob, "/localbus/e1-wan", "rising-edge-sync-pulse",
  80                          sync, strlen(sync), 1);
  81
  82         return 0;
  83 }
  84
  85 int checkboard(void)
  86 {
  87         serial_puts("BOARD: MCR3000 CSSI\n");
  88
  89         return 0;
  90 }
  91
  92 int dram_init(void)
  93 {
  94         immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
  95         memctl8xx_t __iomem *memctl = &immap->im_memctl;
  96
  97         printf("UPMA init for SDRAM (CAS latency 2), ");
  98         printf("init address 0x%08x, size ", (int)dram_init);
  99         /* Configure UPMA for cs1 */
 100         upmconfig(UPMA, (uint *)cs1_dram_table_66,
 101                   sizeof(cs1_dram_table_66) / sizeof(uint));
 102         udelay(10);
 103         out_be16(&memctl->memc_mptpr, 0x0200);
 104         out_be32(&memctl->memc_mamr, 0x14904000);
 105         udelay(10);
 106         out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM);
 107         out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM);
 108         udelay(10);
 109         out_be32(&memctl->memc_mcr, 0x80002830);
 110         out_be32(&memctl->memc_mar, 0x00000088);
 111         out_be32(&memctl->memc_mcr, 0x80002038);
 112         udelay(200);
 113
 114         gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 115                                     SDRAM_MAX_SIZE);
 116
 117         return 0;
 118 }
 119
 120 int misc_init_r(void)
 121 {
 122         immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
 123         iop8xx_t __iomem *iop = &immr->im_ioport;
 124
 125         /* Set port C13 as GPIO (BTN_ACQ_AL) */
 126         clrbits_be16(&iop->iop_pcpar, 0x4);
 127         clrbits_be16(&iop->iop_pcdir, 0x4);
 128
 129         /* if BTN_ACQ_AL is pressed then bootdelay is changed to 60 second */
 130         if ((in_be16(&iop->iop_pcdat) & 0x0004) == 0)
 131                 env_set("bootdelay", "60");
 132
 133         return 0;
 134 }
 135
 136 int board_early_init_f(void)
 137 {
 138         immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
 139
 140         /*
 141          * Erase FPGA(s) for reboot
 142          */
 143         clrbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA down */
 144         setbits_be32(&immr->im_cpm.cp_pbdir, 0x00020000); /* PROGFPGA output */
 145         udelay(1);                              /* Wait more than 300ns */
 146         setbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA up */
 147
 148         return 0;
 149 }
 150
 151 int board_early_init_r(void)
 152 {
 153         struct udevice *watchdog_dev = NULL;
 154
 155         if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
 156                 puts("Cannot find watchdog!\n");
 157         } else {
 158                 puts("Enabling watchdog.\n");
 159                 wdt_start(watchdog_dev, 0xffff, 0);
 160         }
 161
 162         return 0;
 163 }