3 * Tolunay Orkun, Nextio Inc., torkun@nextio.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/u-boot.h>
25 #include <asm/processor.h>
29 #include <405gp_enet.h>
32 * Configuration data for AMIS FS6377-01 Programmable 3-PLL Clock Generator
34 * CLKA output => Epson LCD Controller
35 * CLKB output => Not Connected
36 * CLKC output => Ethernet
37 * CLKD output => UART external clock
39 * Note: these values are obtained from device after init by micromonitor
41 uchar pll_fs6377_regs[16] = {
42 0x28, 0xef, 0x53, 0x03, 0x4b, 0x80, 0x32, 0x80,
43 0x94, 0x32, 0x80, 0xd4, 0x56, 0xf6, 0xf6, 0xe0 };
46 * pll_init: Initialize AMIS IC FS6377-01 PLL
48 * PLL supplies Epson LCD Clock, Ethernet Clock and UART external clock
53 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
55 return i2c_write(CFG_I2C_PLL_ADDR, 0, 1,
56 (uchar *) pll_fs6377_regs, sizeof(pll_fs6377_regs));
60 * board_pre_init: do any preliminary board initialization
63 int board_pre_init(void)
65 /* initialize PLL so UART, LCD, Ethernet clocked at correctly */
69 /*-------------------------------------------------------------------------+
70 | Interrupt controller setup for the Walnut board.
71 | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
72 | IRQ 16 405GP internally generated; active low; level sensitive
74 | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
75 | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
76 | IRQ 27 (EXT IRQ 2) Not Used
77 | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
78 | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
79 | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
80 | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
81 | Note for Walnut board:
82 | An interrupt taken for the FPGA (IRQ 25) indicates that either
83 | the Mouse, Keyboard, IRDA, or External Expansion caused the
84 | interrupt. The FPGA must be read to determine which device
85 | caused the interrupt. The default setting of the FPGA clears
87 +-------------------------------------------------------------------------*/
89 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
90 mtdcr (uicer, 0x00000000); /* disable all ints */
91 mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
92 mtdcr (uicpr, 0xFFFFFF83); /* set int polarities */
93 mtdcr (uictr, 0x10000000); /* set int trigger levels */
94 mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
95 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
97 mtebc (epcr, 0xa8400000); /* EBC always driven */
99 return 0; /* success */
103 * checkboard: identify/verify the board we are running
105 * Remark: we just assume it is correct board here!
110 printf("BOARD: Cogent CSB272\n");
112 return 0; /* success */
116 * initram: Determine the size of mounted DRAM
118 * Size is determined by reading SDRAM configuration registers as
119 * configured by initialization code
122 long initdram (int board_type)
130 mtdcr (memcfga, mem_mb0cf);
131 tmp = mfdcr (memcfgd);
132 if (tmp & 0x00000001) {
133 bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
134 tot_size += bank_size;
137 mtdcr (memcfga, mem_mb1cf);
138 tmp = mfdcr (memcfgd);
139 if (tmp & 0x00000001) {
140 bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
141 tot_size += bank_size;
144 mtdcr (memcfga, mem_mb2cf);
145 tmp = mfdcr (memcfgd);
146 if (tmp & 0x00000001) {
147 bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
148 tot_size += bank_size;
151 mtdcr (memcfga, mem_mb3cf);
152 tmp = mfdcr (memcfgd);
153 if (tmp & 0x00000001) {
154 bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
155 tot_size += bank_size;
162 * last_stage_init: final configurations (such as PHY etc)
165 int last_stage_init(void)
167 /* initialize the PHY */
168 miiphy_reset(CONFIG_PHY_ADDR);
169 miiphy_write(CONFIG_PHY_ADDR, PHY_BMCR,
170 PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); /* AUTO neg */
171 miiphy_write(CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08); /* LEDs */
173 return 0; /* success */