2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
5 /*----------------------------------------------------------------------------- */
6 /* Function: ext_bus_cntlr_init */
7 /* Description: Initializes the External Bus Controller for the external */
8 /* peripherals. IMPORTANT: For pass1 this code must run from */
9 /* cache since you can not reliably change a peripheral banks */
10 /* timing register (pbxap) while running code from that bank. */
11 /* For ex., since we are running from ROM on bank 0, we can NOT */
12 /* execute the code that modifies bank 0 timings from ROM, so */
13 /* we run it from cache. */
14 /* Bank 0 - Flash and SRAM */
15 /* Bank 1 - NVRAM/RTC */
16 /* Bank 2 - Keyboard/Mouse controller */
17 /* Bank 3 - IR controller */
18 /* Bank 4 - not used */
19 /* Bank 5 - not used */
20 /* Bank 6 - not used */
21 /* Bank 7 - FPGA registers */
22 /*-----------------------------------------------------------------------------#include <config.h> */
23 #include <asm/ppc4xx.h>
25 #include <ppc_asm.tmpl>
28 #include <asm/cache.h>
31 /* CRAY - L1: only nominally a 'walnut', since ext.Bus.Cntlr is all empty */
32 /* except for #1 which we use for DMA'ing to IOCA-like things, so the */
33 /* control registers to set that up are determined by what we've */
34 /* empirically discovered work there. */
36 .globl ext_bus_cntlr_init
38 mflr r4 /* save link register */
41 mflr r3 /* get address of ..getAddr */
42 mtlr r4 /* restore link register */
43 addi r4,0,14 /* set ctr to 10; used to prefetch */
44 mtctr r4 /* 10 cache lines to fit this function */
45 /* in cache (gives us 8x10=80 instrctns) */
47 icbt r0,r3 /* prefetch cache line for addr in r3 */
48 addi r3,r3,32 /* move to next cache line */
49 bdnz ..ebcloop /* continue for 10 cache lines */
51 /*------------------------------------------------------------------- */
52 /* Delay to ensure all accesses to ROM are complete before changing */
53 /* bank 0 timings. 200usec should be enough. */
54 /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
55 /*------------------------------------------------------------------- */
57 ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
60 bdnz ..spinlp /* spin loop */
63 /*---------------------------------------------------------------------- */
64 /* Peripheral Bank 0 (Flash) initialization */
65 /*---------------------------------------------------------------------- */
66 /* 0x7F8FFE80 slowest boot */
75 addis r4,0,0xFFC5 /* BAS=0xFFC,BS=0x4(4MB),BU=0x3(R/W), */
76 ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
81 /*---------------------------------------------------------------------- */
82 /* Peripheral Bank 1 (NVRAM/RTC) initialization */
83 /* CRAY:the L1 has NOT this bank, it is tied to SV2/IOCA/etc/ instead */
84 /* and we do DMA on it. The ConfigurationRegister part is threfore */
85 /* almost arbitrary, except that our linux driver needs to know the */
86 /* address, but it can query, it.. */
88 /* The AccessParameter is CRITICAL, */
89 /* thouch, since it needs to agree with the electrical timings on the */
90 /* IOCA parallel interface. That value is: 0x0185,4380 */
91 /* BurstModeEnable BME=0 */
92 /* TransferWait TWT=3 */
93 /* ChipSelectOnTiming CSN=1 */
94 /* OutputEnableOnTimimg OEN=1 */
95 /* WriteByteEnableOnTiming WBN=1 */
96 /* WriteByteEnableOffTiming WBF=0 */
97 /* TransferHold TH=1 */
98 /* ReadyEnable RE=1 */
99 /* SampleOnReady SOR=1 */
100 /* ByteEnableMode BEM=0 */
101 /* ParityEnable PEN=0 */
102 /* all reserved bits=0 */
103 /*---------------------------------------------------------------------- */
104 /*---------------------------------------------------------------------- */
106 mtdcr EBC0_CFGADDR,r4
107 addis r4,0,0x0185 /* hiword */
108 ori r4,r4,0x4380 /* loword */
109 mtdcr EBC0_CFGDATA,r4
112 mtdcr EBC0_CFGADDR,r4
113 addis r4,0,0xF001 /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */
114 ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
115 mtdcr EBC0_CFGDATA,r4