3 * Corscience GmbH & Co. KG, <www.corscience.de>
4 * Thomas Weber <weber@corscience.de>
5 * Sunil Kumar <sunilsaini05@gmail.com>
6 * Shashi Ranjan <shashiranjanmca05@gmail.com>
8 * Derived from Devkit8000 code by
9 * Frederik Kriewitz <frederik@kriewitz.eu>
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm/arch/mmc_host_def.h>
33 #include <asm/arch/mux.h>
34 #include <asm/arch/sys_proto.h>
35 #include <asm/arch/mem.h>
36 #include "tricorder.h"
38 DECLARE_GLOBAL_DATA_PTR;
42 * Description: Early hardware init.
46 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
48 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
54 * Routine: misc_init_r
55 * Description: Configure board specific parts
60 #ifdef CONFIG_TWL4030_LED
61 twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
70 * Routine: set_muxconf_regs
71 * Description: Setting up the configuration Mux registers specific to the
72 * hardware. Many pins need to be moved from protect to primary
75 void set_muxconf_regs(void)
80 #if defined(CONFIG_GENERIC_MMC) && !(defined(CONFIG_SPL_BUILD))
81 int board_mmc_init(bd_t *bis)
83 return omap_mmc_init(0, 0, 0);
88 * Routine: get_board_mem_timings
89 * Description: If we use SPL then there is no x-loader nor config header
90 * so we have to setup the DDR timings ourself on the first bank. This
91 * provides the timing values back to the function that configures
92 * the memory. We have either one or two banks of 128MB DDR.
94 void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
97 /* General SDRC config */
98 *mcfg = MICRON_V_MCFG_165(128 << 20);
99 *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
102 *ctrla = MICRON_V_ACTIMA_165;
103 *ctrlb = MICRON_V_ACTIMB_165;
104 *mr = MICRON_V_MR_165;