board/congatec/cgtqmx6eval/cgtqmx6eval.c

   1 /*
   2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   3  * Based on mx6qsabrelite.c file
   4  * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
   5  * Leo Sartre, <lsartre@adeneo-embedded.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/arch/iomux.h>
  15 #include <asm/arch/mx6-pins.h>
  16 #include <asm/gpio.h>
  17 #include <asm/imx-common/iomux-v3.h>
  18 #include <asm/imx-common/boot_mode.h>
  19 #include <asm/imx-common/mxc_i2c.h>
  20 #include <asm/arch/mxc_hdmi.h>
  21 #include <asm/arch/crm_regs.h>
  22 #include <mmc.h>
  23 #include <fsl_esdhc.h>
  24 #include <i2c.h>
  25 #include <power/pmic.h>
  26 #include <power/pfuze100_pmic.h>
  27 #include <linux/fb.h>
  28 #include <ipu_pixfmt.h>
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |\
  33         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  34
  35 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |\
  36         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  37
  38 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
  39         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  40         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
  41         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  42
  43 #define MX6Q_QMX6_PFUZE_MUX             IMX_GPIO_NR(6, 9)
  44
  45 int dram_init(void)
  46 {
  47         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  48
  49         return 0;
  50 }
  51
  52 static iomux_v3_cfg_t const uart2_pads[] = {
  53         MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  54         MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  55 };
  56
  57 static iomux_v3_cfg_t const usdhc2_pads[] = {
  58         MX6_PAD_SD2_CLK__SD2_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  59         MX6_PAD_SD2_CMD__SD2_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  60         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  61         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  62         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  63         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  64         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  65 };
  66
  67 static iomux_v3_cfg_t const usdhc3_pads[] = {
  68         MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  69         MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  70         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  71         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  72         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  73         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  74         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  75         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  76         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  77         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  78         MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  79 };
  80
  81 static iomux_v3_cfg_t const usdhc4_pads[] = {
  82         MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  83         MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  84         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  85         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  86         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  87         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  88         MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  89         MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  90         MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  91         MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  92         MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  93 };
  94
  95 static iomux_v3_cfg_t const usb_otg_pads[] = {
  96         MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  97         MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
  98 };
  99
 100 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 101 struct i2c_pads_info i2c_pad_info1 = {
 102         .scl = {
 103                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
 104                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
 105                 .gp = IMX_GPIO_NR(4, 12)
 106         },
 107         .sda = {
 108                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
 109                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 110                 .gp = IMX_GPIO_NR(4, 13)
 111         }
 112 };
 113
 114 #define I2C_PMIC        1       /* I2C2 port is used to connect to the PMIC */
 115
 116 struct interface_level {
 117         char *name;
 118         uchar value;
 119 };
 120
 121 static struct interface_level mipi_levels[] = {
 122         {"0V0", 0x00},
 123         {"2V5", 0x17},
 124 };
 125
 126 /* setup board specific PMIC */
 127 int power_init_board(void)
 128 {
 129         struct pmic *p;
 130         u32 id1, id2, i;
 131         int ret;
 132         char const *lv_mipi;
 133
 134         /* configure I2C multiplexer */
 135         gpio_direction_output(MX6Q_QMX6_PFUZE_MUX, 1);
 136
 137         power_pfuze100_init(I2C_PMIC);
 138         p = pmic_get("PFUZE100");
 139         if (!p)
 140                 return -EINVAL;
 141
 142         ret = pmic_probe(p);
 143         if (ret)
 144                 return ret;
 145
 146         pmic_reg_read(p, PFUZE100_DEVICEID, &id1);
 147         pmic_reg_read(p, PFUZE100_REVID, &id2);
 148         printf("PFUZE100 Rev. [%02x/%02x] detected\n", id1, id2);
 149
 150         if (id2 >= 0x20)
 151                 return 0;
 152
 153         /* set level of MIPI if specified */
 154         lv_mipi = getenv("lv_mipi");
 155         if (lv_mipi)
 156                 return 0;
 157
 158         for (i = 0; i < ARRAY_SIZE(mipi_levels); i++) {
 159                 if (!strcmp(mipi_levels[i].name, lv_mipi)) {
 160                         printf("set MIPI level %s\n",
 161                                mipi_levels[i].name);
 162                         ret = pmic_reg_write(p, PFUZE100_VGEN4VOL,
 163                                              mipi_levels[i].value);
 164                         if (ret)
 165                                 return ret;
 166                 }
 167         }
 168
 169         return 0;
 170 }
 171
 172 static void setup_iomux_uart(void)
 173 {
 174         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 175 }
 176
 177 #ifdef CONFIG_FSL_ESDHC
 178 static struct fsl_esdhc_cfg usdhc_cfg[] = {
 179         {USDHC2_BASE_ADDR},
 180         {USDHC3_BASE_ADDR},
 181         {USDHC4_BASE_ADDR},
 182 };
 183
 184 int board_mmc_getcd(struct mmc *mmc)
 185 {
 186         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 187         int ret = 0;
 188
 189         switch (cfg->esdhc_base) {
 190         case USDHC2_BASE_ADDR:
 191                 gpio_direction_input(IMX_GPIO_NR(1, 4));
 192                 ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
 193                 break;
 194         case USDHC3_BASE_ADDR:
 195                 ret = 1;        /* eMMC is always present */
 196                 break;
 197         case USDHC4_BASE_ADDR:
 198                 gpio_direction_input(IMX_GPIO_NR(2, 6));
 199                 ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
 200                 break;
 201         default:
 202                 printf("Bad USDHC interface\n");
 203         }
 204
 205         return ret;
 206 }
 207
 208 int board_mmc_init(bd_t *bis)
 209 {
 210         s32 status = 0;
 211         int i;
 212
 213         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 214         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 215         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 216
 217         imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 218         imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 219         imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 220
 221         for (i = 0; i < ARRAY_SIZE(usdhc_cfg); i++) {
 222                 status = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 223                 if (status)
 224                         return status;
 225         }
 226
 227         return 0;
 228 }
 229 #endif
 230
 231 int board_ehci_hcd_init(int port)
 232 {
 233         switch (port) {
 234         case 0:
 235                 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
 236                                                  ARRAY_SIZE(usb_otg_pads));
 237                 /*
 238                  * set daisy chain for otg_pin_id on 6q.
 239                  * for 6dl, this bit is reserved
 240                  */
 241                 imx_iomux_set_gpr_register(1, 13, 1, 1);
 242                 break;
 243         case 1:
 244                 /* nothing to do */
 245                 break;
 246         default:
 247                 printf("Invalid USB port: %d\n", port);
 248                 return -EINVAL;
 249         }
 250
 251         return 0;
 252 }
 253
 254 int board_ehci_power(int port, int on)
 255 {
 256         switch (port) {
 257         case 0:
 258                 break;
 259         case 1:
 260                 gpio_direction_output(IMX_GPIO_NR(5, 5), on);
 261                 break;
 262         default:
 263                 printf("Invalid USB port: %d\n", port);
 264                 return -EINVAL;
 265         }
 266
 267         return 0;
 268 }
 269
 270 struct display_info_t {
 271         int bus;
 272         int addr;
 273         int pixfmt;
 274         int (*detect)(struct display_info_t const *dev);
 275         void (*enable)(struct display_info_t const *dev);
 276         struct fb_videomode mode;
 277 };
 278
 279 static void disable_lvds(struct display_info_t const *dev)
 280 {
 281         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 282
 283         clrbits_le32(&iomux->gpr[2], IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
 284                      IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
 285 }
 286
 287 static void do_enable_hdmi(struct display_info_t const *dev)
 288 {
 289         disable_lvds(dev);
 290         imx_enable_hdmi_phy();
 291 }
 292
 293 static struct display_info_t const displays[] = {
 294 {
 295         .bus = -1,
 296         .addr = 0,
 297         .pixfmt = IPU_PIX_FMT_RGB666,
 298         .detect = NULL,
 299         .enable = NULL,
 300         .mode = {
 301                 .name =
 302                 "Hannstar-XGA",
 303                 .refresh = 60,
 304                 .xres = 1024,
 305                 .yres = 768,
 306                 .pixclock = 15385,
 307                 .left_margin = 220,
 308                 .right_margin = 40,
 309                 .upper_margin = 21,
 310                 .lower_margin = 7,
 311                 .hsync_len = 60,
 312                 .vsync_len = 10,
 313                 .sync = FB_SYNC_EXT,
 314                 .vmode = FB_VMODE_NONINTERLACED } },
 315 {
 316         .bus = -1,
 317         .addr = 0,
 318         .pixfmt = IPU_PIX_FMT_RGB24,
 319         .detect = NULL,
 320         .enable = do_enable_hdmi,
 321         .mode = {
 322                 .name = "HDMI",
 323                 .refresh = 60,
 324                 .xres = 1024,
 325                 .yres = 768,
 326                 .pixclock = 15385,
 327                 .left_margin = 220,
 328                 .right_margin = 40,
 329                 .upper_margin = 21,
 330                 .lower_margin = 7,
 331                 .hsync_len = 60,
 332                 .vsync_len = 10,
 333                 .sync = FB_SYNC_EXT,
 334                 .vmode = FB_VMODE_NONINTERLACED } }
 335 };
 336
 337 int board_video_skip(void)
 338 {
 339         int i;
 340         int ret;
 341         char const *panel = getenv("panel");
 342         if (!panel) {
 343                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
 344                         struct display_info_t const *dev = displays + i;
 345                         if (dev->detect && dev->detect(dev)) {
 346                                 panel = dev->mode.name;
 347                                 printf("auto-detected panel %s\n", panel);
 348                                 break;
 349                         }
 350                 }
 351                 if (!panel) {
 352                         panel = displays[0].mode.name;
 353                         printf("No panel detected: default to %s\n", panel);
 354                         i = 0;
 355                 }
 356         } else {
 357                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
 358                         if (!strcmp(panel, displays[i].mode.name))
 359                                 break;
 360                 }
 361         }
 362         if (i < ARRAY_SIZE(displays)) {
 363                 ret = ipuv3_fb_init(&displays[i].mode, 0, displays[i].pixfmt);
 364                 if (!ret) {
 365                         if (displays[i].enable)
 366                                 displays[i].enable(displays + i);
 367                         printf("Display: %s (%ux%u)\n",
 368                                displays[i].mode.name, displays[i].mode.xres,
 369                                displays[i].mode.yres);
 370                 } else
 371                         printf("LCD %s cannot be configured: %d\n",
 372                                displays[i].mode.name, ret);
 373         } else {
 374                 printf("unsupported panel %s\n", panel);
 375                 return -EINVAL;
 376         }
 377
 378         return 0;
 379 }
 380
 381 static void setup_display(void)
 382 {
 383         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 384         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 385         int reg;
 386
 387         enable_ipu_clock();
 388         imx_setup_hdmi();
 389
 390         /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
 391         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK |
 392                      MXC_CCM_CCGR3_LDB_DI1_MASK);
 393
 394         /* set LDB0, LDB1 clk select to 011/011 */
 395         reg = readl(&mxc_ccm->cs2cdr);
 396         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
 397                  MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 398         reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
 399                 (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 400         writel(reg, &mxc_ccm->cs2cdr);
 401
 402         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV |
 403                      MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV);
 404
 405         setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 <<
 406                      MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET |
 407                      CHSCCDR_CLK_SEL_LDB_DI0 <<
 408                      MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
 409
 410         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 411                 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
 412                 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 413                 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 414                 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 415                 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 416                 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 417                 | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
 418                 | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
 419         writel(reg, &iomux->gpr[2]);
 420
 421         reg = readl(&iomux->gpr[3]);
 422         reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
 423                        IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) |
 424                 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 425                  IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
 426         writel(reg, &iomux->gpr[3]);
 427 }
 428
 429 /*
 430  * Do not overwrite the console
 431  * Use always serial for U-Boot console
 432  */
 433 int overwrite_console(void)
 434 {
 435         return 1;
 436 }
 437
 438 int board_early_init_f(void)
 439 {
 440         setup_iomux_uart();
 441         setup_display();
 442
 443         return 0;
 444 }
 445
 446 int board_init(void)
 447 {
 448         /* address of boot parameters */
 449         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 450
 451         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 452
 453         return 0;
 454 }
 455
 456 int checkboard(void)
 457 {
 458         puts("Board: Conga-QEVAL QMX6 Quad\n");
 459
 460         return 0;
 461 }
 462
 463 #ifdef CONFIG_CMD_BMODE
 464 static const struct boot_mode board_boot_modes[] = {
 465         /* 4 bit bus width */
 466         {"mmc0",        MAKE_CFGVAL(0x50, 0x20, 0x00, 0x00)},
 467         {"mmc1",        MAKE_CFGVAL(0x50, 0x38, 0x00, 0x00)},
 468         {NULL,          0},
 469 };
 470 #endif
 471
 472 int misc_init_r(void)
 473 {
 474 #ifdef CONFIG_CMD_BMODE
 475         add_board_boot_modes(board_boot_modes);
 476 #endif
 477         return 0;
 478 }