board/compulab/cm_t43/cm_t43.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015 Compulab, Ltd.
   4  */
   5
   6 #include <common.h>
   7 #include <i2c.h>
   8 #include <miiphy.h>
   9 #include <cpsw.h>
  10 #include <asm/gpio.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/emif.h>
  13 #include <power/pmic.h>
  14 #include <power/tps65218.h>
  15 #include "board.h"
  16 #include <usb.h>
  17 #include <asm/omap_common.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  22
  23 /* setup board specific PMIC */
  24 int power_init_board(void)
  25 {
  26         struct pmic *p;
  27         uchar tps_status = 0;
  28
  29         power_tps65218_init(I2C_PMIC);
  30         p = pmic_get("TPS65218_PMIC");
  31         if (p && !pmic_probe(p)) {
  32                 puts("PMIC:  TPS65218\n");
  33                 /* We don't care if fseal is locked, but we do need it set */
  34                 tps65218_lock_fseal();
  35                 tps65218_reg_read(TPS65218_STATUS, &tps_status);
  36                 if (!(tps_status & TPS65218_FSEAL))
  37                         printf("WARNING: RTC not backed by battery!\n");
  38         }
  39
  40         return 0;
  41 }
  42
  43 int board_init(void)
  44 {
  45         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  46         gpmc_init();
  47         set_i2c_pin_mux();
  48         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  49         i2c_probe(TPS65218_CHIP_PM);
  50
  51         return 0;
  52 }
  53
  54 int board_usb_init(int index, enum usb_init_type init)
  55 {
  56         enable_usb_clocks(index);
  57         return 0;
  58 }
  59
  60 int board_usb_cleanup(int index, enum usb_init_type init)
  61 {
  62         disable_usb_clocks(index);
  63         return 0;
  64 }
  65
  66 #ifdef CONFIG_DRIVER_TI_CPSW
  67
  68 static void cpsw_control(int enabled)
  69 {
  70         return;
  71 }
  72
  73 static struct cpsw_slave_data cpsw_slaves[] = {
  74         {
  75                 .slave_reg_ofs  = 0x208,
  76                 .sliver_reg_ofs = 0xd80,
  77                 .phy_addr       = 0,
  78                 .phy_if         = PHY_INTERFACE_MODE_RGMII,
  79         },
  80         {
  81                 .slave_reg_ofs  = 0x308,
  82                 .sliver_reg_ofs = 0xdc0,
  83                 .phy_addr       = 1,
  84                 .phy_if         = PHY_INTERFACE_MODE_RGMII,
  85         },
  86 };
  87
  88 static struct cpsw_platform_data cpsw_data = {
  89         .mdio_base              = CPSW_MDIO_BASE,
  90         .cpsw_base              = CPSW_BASE,
  91         .mdio_div               = 0xff,
  92         .channels               = 8,
  93         .cpdma_reg_ofs          = 0x800,
  94         .slaves                 = 2,
  95         .slave_data             = cpsw_slaves,
  96         .ale_reg_ofs            = 0xd00,
  97         .ale_entries            = 1024,
  98         .host_port_reg_ofs      = 0x108,
  99         .hw_stats_reg_ofs       = 0x900,
 100         .bd_ram_ofs             = 0x2000,
 101         .mac_control            = (1 << 5),
 102         .control                = cpsw_control,
 103         .host_port_num          = 0,
 104         .version                = CPSW_CTRL_VERSION_2,
 105 };
 106
 107 #define GPIO_PHY1_RST           170
 108 #define GPIO_PHY2_RST           168
 109
 110 int board_phy_config(struct phy_device *phydev)
 111 {
 112         unsigned short val;
 113
 114         /* introduce tx clock delay */
 115         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 116         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 117         val |= 0x0100;
 118         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 119
 120         if (phydev->drv->config)
 121                 return phydev->drv->config(phydev);
 122
 123         return 0;
 124 }
 125
 126 static void board_phy_init(void)
 127 {
 128         set_mdio_pin_mux();
 129         writel(0x40003, 0x44e10a74); /* Mux pin as clkout2 */
 130         writel(0x10006, 0x44df4108); /* Select EXTDEV as clock source */
 131         writel(0x4, 0x44df2e60); /* Set EXTDEV as MNbypass */
 132
 133         /* For revision A */
 134         writel(0x2000009, 0x44df2e6c);
 135         writel(0x38a, 0x44df2e70);
 136
 137         mdelay(10);
 138
 139         gpio_request(GPIO_PHY1_RST, "phy1_rst");
 140         gpio_request(GPIO_PHY2_RST, "phy2_rst");
 141         gpio_direction_output(GPIO_PHY1_RST, 0);
 142         gpio_direction_output(GPIO_PHY2_RST, 0);
 143         mdelay(2);
 144
 145         gpio_set_value(GPIO_PHY1_RST, 1);
 146         gpio_set_value(GPIO_PHY2_RST, 1);
 147         mdelay(2);
 148 }
 149
 150 int board_eth_init(bd_t *bis)
 151 {
 152         int rv;
 153
 154         set_rgmii_pin_mux();
 155         writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
 156         board_phy_init();
 157
 158         rv = cpsw_register(&cpsw_data);
 159         if (rv < 0)
 160                 printf("Error %d registering CPSW switch\n", rv);
 161
 162         return rv;
 163 }
 164 #endif