board/compulab/cm_fx6/cm_fx6.c

   1 /*
   2  * Board functions for Compulab CM-FX6 board
   3  *
   4  * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
   5  *
   6  * Author: Nikita Kiryanov <nikita@compulab.co.il>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <fsl_esdhc.h>
  13 #include <asm/arch/crm_regs.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include <asm/io.h>
  16 #include "common.h"
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 #ifdef CONFIG_NAND_MXS
  21 static iomux_v3_cfg_t const nand_pads[] = {
  22         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
  23         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
  24         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  25         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  26         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  27         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  28         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  29         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  30         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  31         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  32         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  33         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  34         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
  35         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
  36 };
  37
  38 static void cm_fx6_setup_gpmi_nand(void)
  39 {
  40         SETUP_IOMUX_PADS(nand_pads);
  41         /* Enable clock roots */
  42         enable_usdhc_clk(1, 3);
  43         enable_usdhc_clk(1, 4);
  44
  45         setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
  46                           MXC_CCM_CS2CDR_ENFC_CLK_PRED(1)   |
  47                           MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
  48 }
  49 #else
  50 static void cm_fx6_setup_gpmi_nand(void) {}
  51 #endif
  52
  53 #ifdef CONFIG_FSL_ESDHC
  54 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
  55         {USDHC1_BASE_ADDR},
  56         {USDHC2_BASE_ADDR},
  57         {USDHC3_BASE_ADDR},
  58 };
  59
  60 static enum mxc_clock usdhc_clk[3] = {
  61         MXC_ESDHC_CLK,
  62         MXC_ESDHC2_CLK,
  63         MXC_ESDHC3_CLK,
  64 };
  65
  66 int board_mmc_init(bd_t *bis)
  67 {
  68         int i;
  69
  70         cm_fx6_set_usdhc_iomux();
  71         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  72                 usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]);
  73                 usdhc_cfg[i].max_bus_width = 4;
  74                 fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  75                 enable_usdhc_clk(1, i);
  76         }
  77
  78         return 0;
  79 }
  80 #endif
  81
  82 int board_init(void)
  83 {
  84         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  85         cm_fx6_setup_gpmi_nand();
  86
  87         return 0;
  88 }
  89
  90 int checkboard(void)
  91 {
  92         puts("Board: CM-FX6\n");
  93         return 0;
  94 }
  95
  96 void dram_init_banksize(void)
  97 {
  98         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  99         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 100
 101         switch (gd->ram_size) {
 102         case 0x10000000: /* DDR_16BIT_256MB */
 103                 gd->bd->bi_dram[0].size = 0x10000000;
 104                 gd->bd->bi_dram[1].size = 0;
 105                 break;
 106         case 0x20000000: /* DDR_32BIT_512MB */
 107                 gd->bd->bi_dram[0].size = 0x20000000;
 108                 gd->bd->bi_dram[1].size = 0;
 109                 break;
 110         case 0x40000000:
 111                 if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
 112                         gd->bd->bi_dram[0].size = 0x20000000;
 113                         gd->bd->bi_dram[1].size = 0x20000000;
 114                 } else { /* DDR_64BIT_1GB */
 115                         gd->bd->bi_dram[0].size = 0x40000000;
 116                         gd->bd->bi_dram[1].size = 0;
 117                 }
 118                 break;
 119         case 0x80000000: /* DDR_64BIT_2GB */
 120                 gd->bd->bi_dram[0].size = 0x40000000;
 121                 gd->bd->bi_dram[1].size = 0x40000000;
 122                 break;
 123         case 0xEFF00000: /* DDR_64BIT_4GB */
 124                 gd->bd->bi_dram[0].size = 0x70000000;
 125                 gd->bd->bi_dram[1].size = 0x7FF00000;
 126                 break;
 127         }
 128 }
 129
 130 int dram_init(void)
 131 {
 132         gd->ram_size = imx_ddr_size();
 133         switch (gd->ram_size) {
 134         case 0x10000000:
 135         case 0x20000000:
 136         case 0x40000000:
 137         case 0x80000000:
 138                 break;
 139         case 0xF0000000:
 140                 gd->ram_size -= 0x100000;
 141                 break;
 142         default:
 143                 printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
 144                 return -1;
 145         }
 146
 147         return 0;
 148 }