board/compulab/cm_fx6/cm_fx6.c

   1 /*
   2  * Board functions for Compulab CM-FX6 board
   3  *
   4  * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
   5  *
   6  * Author: Nikita Kiryanov <nikita@compulab.co.il>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <dm.h>
  13 #include <fsl_esdhc.h>
  14 #include <miiphy.h>
  15 #include <netdev.h>
  16 #include <fdt_support.h>
  17 #include <sata.h>
  18 #include <asm/arch/crm_regs.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/arch/iomux.h>
  21 #include <asm/arch/mxc_hdmi.h>
  22 #include <asm/imx-common/mxc_i2c.h>
  23 #include <asm/imx-common/sata.h>
  24 #include <asm/imx-common/video.h>
  25 #include <asm/io.h>
  26 #include <asm/gpio.h>
  27 #include <dm/platform_data/serial_mxc.h>
  28 #include "common.h"
  29 #include "../common/eeprom.h"
  30 #include "../common/common.h"
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 #ifdef CONFIG_SPLASH_SCREEN
  35 static struct splash_location cm_fx6_splash_locations[] = {
  36         {
  37                 .name = "sf",
  38                 .storage = SPLASH_STORAGE_SF,
  39                 .offset = 0x100000,
  40         },
  41 };
  42
  43 int splash_screen_prepare(void)
  44 {
  45         return cl_splash_screen_prepare(cm_fx6_splash_locations,
  46                                         ARRAY_SIZE(cm_fx6_splash_locations));
  47 }
  48 #endif
  49
  50 #ifdef CONFIG_IMX_HDMI
  51 static void cm_fx6_enable_hdmi(struct display_info_t const *dev)
  52 {
  53         imx_enable_hdmi_phy();
  54 }
  55
  56 struct display_info_t const displays[] = {
  57         {
  58                 .bus    = -1,
  59                 .addr   = 0,
  60                 .pixfmt = IPU_PIX_FMT_RGB24,
  61                 .detect = detect_hdmi,
  62                 .enable = cm_fx6_enable_hdmi,
  63                 .mode   = {
  64                         .name           = "HDMI",
  65                         .refresh        = 60,
  66                         .xres           = 1024,
  67                         .yres           = 768,
  68                         .pixclock       = 40385,
  69                         .left_margin    = 220,
  70                         .right_margin   = 40,
  71                         .upper_margin   = 21,
  72                         .lower_margin   = 7,
  73                         .hsync_len      = 60,
  74                         .vsync_len      = 10,
  75                         .sync           = FB_SYNC_EXT,
  76                         .vmode          = FB_VMODE_NONINTERLACED,
  77                 }
  78         },
  79 };
  80 size_t display_count = ARRAY_SIZE(displays);
  81
  82 static void cm_fx6_setup_display(void)
  83 {
  84         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  85         int reg;
  86
  87         enable_ipu_clock();
  88         imx_setup_hdmi();
  89         reg = __raw_readl(&mxc_ccm->CCGR3);
  90         reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK;
  91         writel(reg, &mxc_ccm->CCGR3);
  92 }
  93 #else
  94 static inline void cm_fx6_setup_display(void) {}
  95 #endif /* CONFIG_VIDEO_IPUV3 */
  96
  97 #ifdef CONFIG_DWC_AHSATA
  98 static int cm_fx6_issd_gpios[] = {
  99         /* The order of the GPIOs in the array is important! */
 100         CM_FX6_SATA_LDO_EN,
 101         CM_FX6_SATA_PHY_SLP,
 102         CM_FX6_SATA_NRSTDLY,
 103         CM_FX6_SATA_PWREN,
 104         CM_FX6_SATA_NSTANDBY1,
 105         CM_FX6_SATA_NSTANDBY2,
 106 };
 107
 108 static void cm_fx6_sata_power(int on)
 109 {
 110         int i;
 111
 112         if (!on) { /* tell the iSSD that the power will be removed */
 113                 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1);
 114                 mdelay(10);
 115         }
 116
 117         for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
 118                 gpio_direction_output(cm_fx6_issd_gpios[i], on);
 119                 udelay(100);
 120         }
 121
 122         if (!on) /* for compatibility lower the power loss interrupt */
 123                 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
 124 }
 125
 126 static iomux_v3_cfg_t const sata_pads[] = {
 127         /* SATA PWR */
 128         IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 129         IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 130         IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 131         IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 132         /* SATA CTRL */
 133         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30  | MUX_PAD_CTRL(NO_PAD_CTRL)),
 134         IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 135         IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 136         IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 137         IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 138 };
 139
 140 static int cm_fx6_setup_issd(void)
 141 {
 142         int ret, i;
 143
 144         SETUP_IOMUX_PADS(sata_pads);
 145
 146         for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
 147                 ret = gpio_request(cm_fx6_issd_gpios[i], "sata");
 148                 if (ret)
 149                         return ret;
 150         }
 151
 152         ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int");
 153         if (ret)
 154                 return ret;
 155
 156         return 0;
 157 }
 158
 159 #define CM_FX6_SATA_INIT_RETRIES        10
 160 int sata_initialize(void)
 161 {
 162         int err, i;
 163
 164         /* Make sure this gpio has logical 0 value */
 165         gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
 166         udelay(100);
 167         cm_fx6_sata_power(1);
 168
 169         for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
 170                 err = setup_sata();
 171                 if (err) {
 172                         printf("SATA setup failed: %d\n", err);
 173                         return err;
 174                 }
 175
 176                 udelay(100);
 177
 178                 err = __sata_initialize();
 179                 if (!err)
 180                         break;
 181
 182                 /* There is no device on the SATA port */
 183                 if (sata_port_status(0, 0) == 0)
 184                         break;
 185
 186                 /* There's a device, but link not established. Retry */
 187         }
 188
 189         return err;
 190 }
 191
 192 int sata_stop(void)
 193 {
 194         __sata_stop();
 195         cm_fx6_sata_power(0);
 196         mdelay(250);
 197
 198         return 0;
 199 }
 200 #else
 201 static int cm_fx6_setup_issd(void) { return 0; }
 202 #endif
 203
 204 #ifdef CONFIG_SYS_I2C_MXC
 205 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
 206                         PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
 207                         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
 208
 209 I2C_PADS(i2c0_pads,
 210          PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 211          PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 212          IMX_GPIO_NR(3, 21),
 213          PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 214          PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 215          IMX_GPIO_NR(3, 28));
 216
 217 I2C_PADS(i2c1_pads,
 218          PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 219          PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 220          IMX_GPIO_NR(4, 12),
 221          PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 222          PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 223          IMX_GPIO_NR(4, 13));
 224
 225 I2C_PADS(i2c2_pads,
 226          PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 227          PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 228          IMX_GPIO_NR(1, 3),
 229          PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 230          PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 231          IMX_GPIO_NR(1, 6));
 232
 233
 234 static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads)
 235 {
 236         int ret;
 237
 238         ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads);
 239         if (ret)
 240                 printf("Warning: I2C%d setup failed: %d\n", busnum, ret);
 241
 242         return ret;
 243 }
 244
 245 static int cm_fx6_setup_i2c(void)
 246 {
 247         int ret = 0, err;
 248
 249         /* i2c<x>_pads are wierd macro variables; we can't use an array */
 250         err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads));
 251         if (err)
 252                 ret = err;
 253         err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads));
 254         if (err)
 255                 ret = err;
 256         err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads));
 257         if (err)
 258                 ret = err;
 259
 260         return ret;
 261 }
 262 #else
 263 static int cm_fx6_setup_i2c(void) { return 0; }
 264 #endif
 265
 266 #ifdef CONFIG_USB_EHCI_MX6
 267 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
 268                         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
 269                         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
 270 #define MX6_USBNC_BASEADDR      0x2184800
 271 #define USBNC_USB_H1_PWR_POL    (1 << 9)
 272
 273 static int cm_fx6_setup_usb_host(void)
 274 {
 275         int err;
 276
 277         err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
 278         if (err)
 279                 return err;
 280
 281         SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL));
 282         SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL));
 283
 284         return 0;
 285 }
 286
 287 static int cm_fx6_setup_usb_otg(void)
 288 {
 289         int err;
 290         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 291
 292         err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
 293         if (err) {
 294                 printf("USB OTG pwr gpio request failed: %d\n", err);
 295                 return err;
 296         }
 297
 298         SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL));
 299         SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID |
 300                                                 MUX_PAD_CTRL(WEAK_PULLDOWN));
 301         clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK);
 302         /* disable ext. charger detect, or it'll affect signal quality at dp. */
 303         return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
 304 }
 305
 306 int board_ehci_hcd_init(int port)
 307 {
 308         int ret;
 309         u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4);
 310
 311         /* Only 1 host controller in use. port 0 is OTG & needs no attention */
 312         if (port != 1)
 313                 return 0;
 314
 315         /* Set PWR polarity to match power switch's enable polarity */
 316         setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
 317         ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
 318         if (ret)
 319                 return ret;
 320
 321         udelay(10);
 322         ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
 323         if (ret)
 324                 return ret;
 325
 326         mdelay(1);
 327
 328         return 0;
 329 }
 330
 331 int board_ehci_power(int port, int on)
 332 {
 333         if (port == 0)
 334                 return gpio_direction_output(SB_FX6_USB_OTG_PWR, on);
 335
 336         return 0;
 337 }
 338 #else
 339 static int cm_fx6_setup_usb_otg(void) { return 0; }
 340 static int cm_fx6_setup_usb_host(void) { return 0; }
 341 #endif
 342
 343 #ifdef CONFIG_FEC_MXC
 344 #define ENET_PAD_CTRL           (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
 345                                  PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 346
 347 static int mx6_rgmii_rework(struct phy_device *phydev)
 348 {
 349         unsigned short val;
 350
 351         /* Ar8031 phy SmartEEE feature cause link status generates glitch,
 352          * which cause ethernet link down/up issue, so disable SmartEEE
 353          */
 354         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
 355         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
 356         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
 357         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 358         val &= ~(0x1 << 8);
 359         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 360
 361         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 362         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 363         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 364         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 365
 366         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 367         val &= 0xffe3;
 368         val |= 0x18;
 369         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 370
 371         /* introduce tx clock delay */
 372         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 373         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 374         val |= 0x0100;
 375         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 376
 377         return 0;
 378 }
 379
 380 int board_phy_config(struct phy_device *phydev)
 381 {
 382         mx6_rgmii_rework(phydev);
 383
 384         if (phydev->drv->config)
 385                 return phydev->drv->config(phydev);
 386
 387         return 0;
 388 }
 389
 390 static iomux_v3_cfg_t const enet_pads[] = {
 391         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 392         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 393         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 394         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 395         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 396         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 397         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 398         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 399         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 400         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 401         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 402         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 403         IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 404         IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 405         IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)),
 406         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK  |
 407                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 408         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
 409                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 410         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
 411                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 412 };
 413
 414 static int handle_mac_address(char *env_var, uint eeprom_bus)
 415 {
 416         unsigned char enetaddr[6];
 417         int rc;
 418
 419         rc = eth_getenv_enetaddr(env_var, enetaddr);
 420         if (rc)
 421                 return 0;
 422
 423         rc = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus);
 424         if (rc)
 425                 return rc;
 426
 427         if (!is_valid_ether_addr(enetaddr))
 428                 return -1;
 429
 430         return eth_setenv_enetaddr(env_var, enetaddr);
 431 }
 432
 433 #define SB_FX6_I2C_EEPROM_BUS   0
 434 #define NO_MAC_ADDR             "No MAC address found for %s\n"
 435 int board_eth_init(bd_t *bis)
 436 {
 437         int err;
 438
 439         if (handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS))
 440                 printf(NO_MAC_ADDR, "primary NIC");
 441
 442         if (handle_mac_address("eth1addr", SB_FX6_I2C_EEPROM_BUS))
 443                 printf(NO_MAC_ADDR, "secondary NIC");
 444
 445         SETUP_IOMUX_PADS(enet_pads);
 446         /* phy reset */
 447         err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst");
 448         if (err)
 449                 printf("Etnernet NRST gpio request failed: %d\n", err);
 450         gpio_direction_output(CM_FX6_ENET_NRST, 0);
 451         udelay(500);
 452         gpio_set_value(CM_FX6_ENET_NRST, 1);
 453         enable_enet_clk(1);
 454         return cpu_eth_init(bis);
 455 }
 456 #endif
 457
 458 #ifdef CONFIG_NAND_MXS
 459 static iomux_v3_cfg_t const nand_pads[] = {
 460         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 461         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 462         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 463         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
 464         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 465         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 466         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 467         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 468         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 469         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 470         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 471         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 472         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 473         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 474 };
 475
 476 static void cm_fx6_setup_gpmi_nand(void)
 477 {
 478         SETUP_IOMUX_PADS(nand_pads);
 479         /* Enable clock roots */
 480         enable_usdhc_clk(1, 3);
 481         enable_usdhc_clk(1, 4);
 482
 483         setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
 484                           MXC_CCM_CS2CDR_ENFC_CLK_PRED(1)   |
 485                           MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
 486 }
 487 #else
 488 static void cm_fx6_setup_gpmi_nand(void) {}
 489 #endif
 490
 491 #ifdef CONFIG_FSL_ESDHC
 492 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
 493         {USDHC1_BASE_ADDR},
 494         {USDHC2_BASE_ADDR},
 495         {USDHC3_BASE_ADDR},
 496 };
 497
 498 static enum mxc_clock usdhc_clk[3] = {
 499         MXC_ESDHC_CLK,
 500         MXC_ESDHC2_CLK,
 501         MXC_ESDHC3_CLK,
 502 };
 503
 504 int board_mmc_init(bd_t *bis)
 505 {
 506         int i;
 507
 508         cm_fx6_set_usdhc_iomux();
 509         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 510                 usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]);
 511                 usdhc_cfg[i].max_bus_width = 4;
 512                 fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 513                 enable_usdhc_clk(1, i);
 514         }
 515
 516         return 0;
 517 }
 518 #endif
 519
 520 #ifdef CONFIG_MXC_SPI
 521 int cm_fx6_setup_ecspi(void)
 522 {
 523         cm_fx6_set_ecspi_iomux();
 524         return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0");
 525 }
 526 #else
 527 int cm_fx6_setup_ecspi(void) { return 0; }
 528 #endif
 529
 530 #ifdef CONFIG_OF_BOARD_SETUP
 531 int ft_board_setup(void *blob, bd_t *bd)
 532 {
 533         uint8_t enetaddr[6];
 534
 535         /* MAC addr */
 536         if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
 537                 fdt_find_and_setprop(blob,
 538                                      "/soc/aips-bus@02100000/ethernet@02188000",
 539                                      "local-mac-address", enetaddr, 6, 1);
 540         }
 541
 542         if (eth_getenv_enetaddr("eth1addr", enetaddr)) {
 543                 fdt_find_and_setprop(blob, "/eth@pcie", "local-mac-address",
 544                                      enetaddr, 6, 1);
 545         }
 546
 547         return 0;
 548 }
 549 #endif
 550
 551 int board_init(void)
 552 {
 553         int ret;
 554
 555         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 556         cm_fx6_setup_gpmi_nand();
 557
 558         ret = cm_fx6_setup_ecspi();
 559         if (ret)
 560                 printf("Warning: ECSPI setup failed: %d\n", ret);
 561
 562         ret = cm_fx6_setup_usb_otg();
 563         if (ret)
 564                 printf("Warning: USB OTG setup failed: %d\n", ret);
 565
 566         ret = cm_fx6_setup_usb_host();
 567         if (ret)
 568                 printf("Warning: USB host setup failed: %d\n", ret);
 569
 570         /*
 571          * cm-fx6 may have iSSD not assembled and in this case it has
 572          * bypasses for a (m)SATA socket on the baseboard. The socketed
 573          * device is not controlled by those GPIOs. So just print a warning
 574          * if the setup fails.
 575          */
 576         ret = cm_fx6_setup_issd();
 577         if (ret)
 578                 printf("Warning: iSSD setup failed: %d\n", ret);
 579
 580         /* Warn on failure but do not abort boot */
 581         ret = cm_fx6_setup_i2c();
 582         if (ret)
 583                 printf("Warning: I2C setup failed: %d\n", ret);
 584
 585         cm_fx6_setup_display();
 586
 587         return 0;
 588 }
 589
 590 int checkboard(void)
 591 {
 592         puts("Board: CM-FX6\n");
 593         return 0;
 594 }
 595
 596 void dram_init_banksize(void)
 597 {
 598         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 599         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 600
 601         switch (gd->ram_size) {
 602         case 0x10000000: /* DDR_16BIT_256MB */
 603                 gd->bd->bi_dram[0].size = 0x10000000;
 604                 gd->bd->bi_dram[1].size = 0;
 605                 break;
 606         case 0x20000000: /* DDR_32BIT_512MB */
 607                 gd->bd->bi_dram[0].size = 0x20000000;
 608                 gd->bd->bi_dram[1].size = 0;
 609                 break;
 610         case 0x40000000:
 611                 if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
 612                         gd->bd->bi_dram[0].size = 0x20000000;
 613                         gd->bd->bi_dram[1].size = 0x20000000;
 614                 } else { /* DDR_64BIT_1GB */
 615                         gd->bd->bi_dram[0].size = 0x40000000;
 616                         gd->bd->bi_dram[1].size = 0;
 617                 }
 618                 break;
 619         case 0x80000000: /* DDR_64BIT_2GB */
 620                 gd->bd->bi_dram[0].size = 0x40000000;
 621                 gd->bd->bi_dram[1].size = 0x40000000;
 622                 break;
 623         case 0xEFF00000: /* DDR_64BIT_4GB */
 624                 gd->bd->bi_dram[0].size = 0x70000000;
 625                 gd->bd->bi_dram[1].size = 0x7FF00000;
 626                 break;
 627         }
 628 }
 629
 630 int dram_init(void)
 631 {
 632         gd->ram_size = imx_ddr_size();
 633         switch (gd->ram_size) {
 634         case 0x10000000:
 635         case 0x20000000:
 636         case 0x40000000:
 637         case 0x80000000:
 638                 break;
 639         case 0xF0000000:
 640                 gd->ram_size -= 0x100000;
 641                 break;
 642         default:
 643                 printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
 644                 return -1;
 645         }
 646
 647         return 0;
 648 }
 649
 650 u32 get_board_rev(void)
 651 {
 652         return cl_eeprom_get_board_rev();
 653 }
 654
 655 static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = {
 656         .reg = (struct mxc_uart *)UART4_BASE,
 657 };
 658
 659 U_BOOT_DEVICE(cm_fx6_serial) = {
 660         .name   = "serial_mxc",
 661         .platdata = &cm_fx6_mxc_serial_plat,
 662 };