2 * Board functions for Compulab CM-FX6 board
4 * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
6 * Author: Nikita Kiryanov <nikita@compulab.co.il>
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <fsl_esdhc.h>
16 #include <fdt_support.h>
18 #include <serial_mxc.h>
19 #include <asm/arch/crm_regs.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/arch/iomux.h>
22 #include <asm/imx-common/mxc_i2c.h>
23 #include <asm/imx-common/sata.h>
27 #include "../common/eeprom.h"
29 DECLARE_GLOBAL_DATA_PTR;
31 #ifdef CONFIG_DWC_AHSATA
32 static int cm_fx6_issd_gpios[] = {
33 /* The order of the GPIOs in the array is important! */
37 CM_FX6_SATA_NSTANDBY1,
38 CM_FX6_SATA_NSTANDBY2,
42 static void cm_fx6_sata_power(int on)
46 if (!on) { /* tell the iSSD that the power will be removed */
47 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1);
51 for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
52 gpio_direction_output(cm_fx6_issd_gpios[i], on);
56 if (!on) /* for compatibility lower the power loss interrupt */
57 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
60 static iomux_v3_cfg_t const sata_pads[] = {
62 IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
63 IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
64 IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
65 IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
67 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
68 IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
69 IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
70 IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
71 IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
74 static int cm_fx6_setup_issd(void)
78 SETUP_IOMUX_PADS(sata_pads);
80 for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
81 ret = gpio_request(cm_fx6_issd_gpios[i], "sata");
86 ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int");
93 #define CM_FX6_SATA_INIT_RETRIES 10
94 int sata_initialize(void)
98 /* Make sure this gpio has logical 0 value */
99 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
102 cm_fx6_sata_power(0);
104 cm_fx6_sata_power(1);
106 for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
109 printf("SATA setup failed: %d\n", err);
115 err = __sata_initialize();
119 /* There is no device on the SATA port */
120 if (sata_port_status(0, 0) == 0)
123 /* There's a device, but link not established. Retry */
129 static int cm_fx6_setup_issd(void) { return 0; }
132 #ifdef CONFIG_SYS_I2C_MXC
133 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
134 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
135 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
138 PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
139 PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL),
141 PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
142 PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL),
146 PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
147 PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL),
149 PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
150 PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL),
154 PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
155 PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL),
157 PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
158 PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
162 static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads)
166 ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads);
168 printf("Warning: I2C%d setup failed: %d\n", busnum, ret);
173 static int cm_fx6_setup_i2c(void)
177 /* i2c<x>_pads are wierd macro variables; we can't use an array */
178 err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads));
181 err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads));
184 err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads));
191 static int cm_fx6_setup_i2c(void) { return 0; }
194 #ifdef CONFIG_USB_EHCI_MX6
195 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
196 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
197 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
198 #define MX6_USBNC_BASEADDR 0x2184800
199 #define USBNC_USB_H1_PWR_POL (1 << 9)
201 static int cm_fx6_setup_usb_host(void)
205 err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
209 SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL));
210 SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL));
215 static int cm_fx6_setup_usb_otg(void)
218 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
220 err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
222 printf("USB OTG pwr gpio request failed: %d\n", err);
226 SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL));
227 SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID |
228 MUX_PAD_CTRL(WEAK_PULLDOWN));
229 clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK);
230 /* disable ext. charger detect, or it'll affect signal quality at dp. */
231 return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
234 int board_ehci_hcd_init(int port)
237 u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4);
239 /* Only 1 host controller in use. port 0 is OTG & needs no attention */
243 /* Set PWR polarity to match power switch's enable polarity */
244 setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
245 ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
250 ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
259 int board_ehci_power(int port, int on)
262 return gpio_direction_output(SB_FX6_USB_OTG_PWR, on);
267 static int cm_fx6_setup_usb_otg(void) { return 0; }
268 static int cm_fx6_setup_usb_host(void) { return 0; }
271 #ifdef CONFIG_FEC_MXC
272 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
273 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
275 static int mx6_rgmii_rework(struct phy_device *phydev)
279 /* Ar8031 phy SmartEEE feature cause link status generates glitch,
280 * which cause ethernet link down/up issue, so disable SmartEEE
282 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
283 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
284 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
285 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
287 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
289 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
290 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
291 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
292 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
294 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
297 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
299 /* introduce tx clock delay */
300 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
301 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
303 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
308 int board_phy_config(struct phy_device *phydev)
310 mx6_rgmii_rework(phydev);
312 if (phydev->drv->config)
313 return phydev->drv->config(phydev);
318 static iomux_v3_cfg_t const enet_pads[] = {
319 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
320 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
321 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
322 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
323 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
324 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
325 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
326 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
327 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
328 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
329 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
330 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
331 IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1 | MUX_PAD_CTRL(NO_PAD_CTRL)),
332 IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL)),
333 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)),
334 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
335 MUX_PAD_CTRL(ENET_PAD_CTRL)),
336 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
337 MUX_PAD_CTRL(ENET_PAD_CTRL)),
338 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
339 MUX_PAD_CTRL(ENET_PAD_CTRL)),
342 static int handle_mac_address(void)
344 unsigned char enetaddr[6];
347 rc = eth_getenv_enetaddr("ethaddr", enetaddr);
351 rc = cl_eeprom_read_mac_addr(enetaddr);
355 if (!is_valid_ether_addr(enetaddr))
358 return eth_setenv_enetaddr("ethaddr", enetaddr);
361 int board_eth_init(bd_t *bis)
365 err = handle_mac_address();
367 puts("No MAC address found\n");
369 SETUP_IOMUX_PADS(enet_pads);
371 err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst");
373 printf("Etnernet NRST gpio request failed: %d\n", err);
374 gpio_direction_output(CM_FX6_ENET_NRST, 0);
376 gpio_set_value(CM_FX6_ENET_NRST, 1);
378 return cpu_eth_init(bis);
382 #ifdef CONFIG_NAND_MXS
383 static iomux_v3_cfg_t const nand_pads[] = {
384 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
385 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
386 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
387 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
388 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
389 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
390 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
391 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
392 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
393 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
394 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
395 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
396 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
397 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
400 static void cm_fx6_setup_gpmi_nand(void)
402 SETUP_IOMUX_PADS(nand_pads);
403 /* Enable clock roots */
404 enable_usdhc_clk(1, 3);
405 enable_usdhc_clk(1, 4);
407 setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
408 MXC_CCM_CS2CDR_ENFC_CLK_PRED(1) |
409 MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
412 static void cm_fx6_setup_gpmi_nand(void) {}
415 #ifdef CONFIG_FSL_ESDHC
416 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
422 static enum mxc_clock usdhc_clk[3] = {
428 int board_mmc_init(bd_t *bis)
432 cm_fx6_set_usdhc_iomux();
433 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
434 usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]);
435 usdhc_cfg[i].max_bus_width = 4;
436 fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
437 enable_usdhc_clk(1, i);
444 #ifdef CONFIG_MXC_SPI
445 int cm_fx6_setup_ecspi(void)
447 cm_fx6_set_ecspi_iomux();
448 return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0");
451 int cm_fx6_setup_ecspi(void) { return 0; }
454 #ifdef CONFIG_OF_BOARD_SETUP
455 void ft_board_setup(void *blob, bd_t *bd)
460 if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
461 fdt_find_and_setprop(blob, "/fec", "local-mac-address",
471 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
472 cm_fx6_setup_gpmi_nand();
474 ret = cm_fx6_setup_ecspi();
476 printf("Warning: ECSPI setup failed: %d\n", ret);
478 ret = cm_fx6_setup_usb_otg();
480 printf("Warning: USB OTG setup failed: %d\n", ret);
482 ret = cm_fx6_setup_usb_host();
484 printf("Warning: USB host setup failed: %d\n", ret);
487 * cm-fx6 may have iSSD not assembled and in this case it has
488 * bypasses for a (m)SATA socket on the baseboard. The socketed
489 * device is not controlled by those GPIOs. So just print a warning
490 * if the setup fails.
492 ret = cm_fx6_setup_issd();
494 printf("Warning: iSSD setup failed: %d\n", ret);
496 /* Warn on failure but do not abort boot */
497 ret = cm_fx6_setup_i2c();
499 printf("Warning: I2C setup failed: %d\n", ret);
506 puts("Board: CM-FX6\n");
510 void dram_init_banksize(void)
512 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
513 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
515 switch (gd->ram_size) {
516 case 0x10000000: /* DDR_16BIT_256MB */
517 gd->bd->bi_dram[0].size = 0x10000000;
518 gd->bd->bi_dram[1].size = 0;
520 case 0x20000000: /* DDR_32BIT_512MB */
521 gd->bd->bi_dram[0].size = 0x20000000;
522 gd->bd->bi_dram[1].size = 0;
525 if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
526 gd->bd->bi_dram[0].size = 0x20000000;
527 gd->bd->bi_dram[1].size = 0x20000000;
528 } else { /* DDR_64BIT_1GB */
529 gd->bd->bi_dram[0].size = 0x40000000;
530 gd->bd->bi_dram[1].size = 0;
533 case 0x80000000: /* DDR_64BIT_2GB */
534 gd->bd->bi_dram[0].size = 0x40000000;
535 gd->bd->bi_dram[1].size = 0x40000000;
537 case 0xEFF00000: /* DDR_64BIT_4GB */
538 gd->bd->bi_dram[0].size = 0x70000000;
539 gd->bd->bi_dram[1].size = 0x7FF00000;
546 gd->ram_size = imx_ddr_size();
547 switch (gd->ram_size) {
554 gd->ram_size -= 0x100000;
557 printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
564 u32 get_board_rev(void)
566 return cl_eeprom_get_board_rev();
569 static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = {
570 .reg = (struct mxc_uart *)UART4_BASE,
573 U_BOOT_DEVICE(cm_fx6_serial) = {
574 .name = "serial_mxc",
575 .platdata = &cm_fx6_mxc_serial_plat,